Lead Analog/Mixed-Signal ASIC Design Engineer

Taara•Sunnyvale, CA

1d•$258,000 - $294,000

About The Position

Taara, born at X (Google’s Moonshot Factory), is working to connect people without abundant and affordable internet through high-throughput, long-range free-space optical communication. Its eye-safe laser links transmit high-speed data wirelessly between terminals. The team develops wireless optical communication systems based on integrated optical phased arrays. The Lead Analog/Mixed-Signal ASIC Design Engineer will lead ASIC tape-out efforts, own the ASIC top-level architecture, and drive the delivery and validation of ASIC dies for co-integrated electronic and photonic modules. The role combines hands-on AMS ASIC design and layout with coordination of a small team of ASIC design and layout engineers. The successful candidate will bring extensive ASIC design and layout experience, including ownership of top-level ASIC tape-outs at leading commercial foundries, and deep expertise in high-precision AMS circuits, high-speed wireline and silicon-photonics interface circuits, or both. The engineer will own and deliver custom ASICs for integration with large-scale photonic integrated circuits, contribute to ASIC design and layout, system-level optimization, and product strategy, and help advance the company’s optical communication technology. The role is suited to someone motivated by challenging, high-impact work in a small, dynamic team and comfortable with ambiguity.

Requirements

Ph.D. in Electrical Engineering or a related field.
At least 10 years of relevant industry experience, with demonstrated achievements in analog/mixed-signal circuit design and implementation in modern CMOS technologies.
Deep design expertise in high-precision circuits, high-speed circuits, or both.
For high-precision designs: experience with ADCs, DACs, bandgap references, voltage regulators, amplifiers, supporting circuitry, and integration and co-simulation of analog and digital circuits for mixed-signal design and verification.
For high-speed designs: experience with optical communication front-end circuits, including modulator drivers and TIAs operating at tens of GHz, and broadband serial-link circuits such as receivers, transmitters, and equalizers.
Experience with electromagnetic design of high-frequency transmission lines, inductors, and other passive elements, if pursuing high-speed design expertise.
Experience owning top-level ASIC architecture and coordinating engineering teams.
Hands-on experience leading multiple ASIC tape-outs at commercial foundries.
Hands-on experience with Design Rule Checks (DRC), Layout Versus Schematic (LVS), Power Integrity (PI), and Signal Integrity (SI) verification.

Nice To Haves

Experience planning and executing verification of large SoCs incorporating complex digital logic and many custom-designed blocks.
Experience with hardware description languages, such as RTL, and RTL-to-GDS design flows using industry-standard EDA tools for synthesis, timing analysis, and place-and-route.
Experience with versioning tools such as SOS and Git.
Experience with commercial layout verification software such as Calibre or equivalent.
Excellent communication and presentation skills, including the ability to work effectively with senior external partners.
Hands-on experience advancing a product from prototype to final production.

Responsibilities

Lead ASIC tape-out efforts and own the ASIC top-level architecture.
Drive the delivery and validation of ASIC dies.
Make hands-on contributions to analog/mixed-signal ASIC design and layout.
Coordinate a small team of ASIC design and layout engineers.
Own and deliver custom ASICs for co-integration with large-scale photonic integrated circuits.
Contribute to system-level optimization and product strategy.
Lead top-level ASIC tape-outs at commercial foundries.