Layout/Mask Design

Apple • Austin, TX

2d

About The Position

Apple Inc. is hiring for a Layout/Mask Design role in Austin, Texas. The position designs complex custom layouts for digital circuits in deep submicron CMOS technologies. The role works with layout leads and circuit designers to review and analyze complex-circuit floorplans, plan and schedule work, negotiate layout tradeoffs, and deliver layouts that meet engineering specifications.

The position runs layout design verification tools, cleans up megacells, interprets LVS, DRC, ERC, and DFM reports, and applies layout corrections using advanced CAD tools and mask-design knowledge. It uses advanced layout techniques and automated place-and-route tools to improve power, performance, and area (PPA), and works with design leads to review EMIR simulations and implement fixes for robust power delivery. The work schedule is 40 hours per week.

Requirements

• Bachelor’s degree or foreign equivalent in Electrical Engineering or a related field.
• At least 2 years of experience in the job offered or a related occupation.
• Experience and/or education using layout floor-planning, standard-cell planning, and hierarchical layout assembly to generate layouts optimized for power, performance, and area.
• Experience resolving issues involving RC delay, electromigration, self-heating, and cross capacitance.
• Ability to recognize failure-prone layout structures and work with designers on solutions, including shielding critical signals, analyzing DFM yields, and addressing LOD effects.
• Experience creating layouts with a robust power-grid (PG) grid using IR simulation tools.
• Ability to collaborate and communicate effectively with cross-functional teams to understand engineering specifications and deliver on time.
• Experience interpreting CALIBRE DRC, ERC, LVS, and DFM reports to complete layouts.
• Experience using CADENCE Virtuoso layout design tools to draw layouts and improve productivity.

Responsibilities

• Design complex custom layouts for digital circuits in deep submicron CMOS technologies.
• Review and analyze complex-circuit floorplans with layout leads and circuit designers.
• Run layout design verification tools and clean up megacells to match engineering specifications.
• Plan and schedule work with layout leads and circuit design teams, and negotiate layout tradeoffs as needed.
• Interpret LVS, DRC, and ERC reports to complete layouts efficiently.
• Use advanced CAD tools and mask-design knowledge to make layout corrections and create robust physical representations of circuits.
• Apply advanced layout techniques to achieve strong PPA for critical designs.
• Review EMIR simulations with the design lead and implement necessary fixes for robust power delivery.
• Use automated place-and-route tools to speed up digital layout execution.

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level