Layout/Mask Designer

Micron • Boise, ID

1d

About The Position

Create physical layouts of transistors, resistors, and capacitors for analog circuits used in developing memory products. Develop layouts that meet process rules and verify that they match schematics. Work on floor planning, routing, and power bus designs. Support the team in establishing IP layout work modes, including layout standardization, co-work flow, and alignment methods to minimize impact. Deliver quality layouts on time, monitor layout quality, pass SPF, confirm with circuit designers, and deliver layout and DBR on time.

Provide IC layout design support through floor planning, custom layout, analog/mixed-signal layout, and full-chip-level layout designs. Perform layout verification, including LVS/DRC/DFM, support, quality checks, and documentation. Complete function blocks with good layout quality following broad instructions. Apply judgment when interpreting results and conducting quantitative analysis. Communicate with engineering teams in India, Japan, and the US to help ensure project success.

Requirements

• Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Knowledge of DRAM circuit functions.
• Experience with IC custom layout for IP layout design.
• Experience with Cadence OA and Caliber verification tools.
• Knowledge of design rule check (DRC) and layout versus schematic (LVS).
• Experience making layout patterns.
• Knowledge of industrial applications of devices and sensors.

Responsibilities

• Create physical layouts of transistors, resistors, and capacitors for analog circuits used in memory product development.
• Build layouts that meet process rules and verify that they match schematics.
• Work on floor planning, routing, and power bus designs.
• Support establishment of IP layout work modes, including layout standardization, co-work flow, and alignment methods to minimize impact.
• Deliver quality layouts on time, monitor layout quality, pass SPF, confirm with circuit designers, and deliver layout and DBR on time.
• Provide IC layout design support for floor planning, custom layout, analog/mixed-signal layout, and full-chip-level layout designs.
• Perform layout verification, including LVS/DRC/DFM, quality checks, and documentation.
• Complete function blocks with good layout quality while following broad instructions.
• Interpret results and conduct quantitative analysis using judgment.
• Communicate with engineering teams in India, Japan, and the US to support project success.

Benefits

• Medical, dental, and vision plans.
• Income protection benefits in case of illness or injury.
• Paid family leave.
• Paid time off.
• Paid holidays.

What This Job Offers

• Job Type: Full-time