Principal FinFET IC Mask Layout Designer – TeraWave

BLUE ORIGIN•San Diego, CA

1d•$269,175 - $376,844•Onsite

About The Position

Blue Origin is seeking an experienced Analog/mixed-signal IC mask layout designer to participate in and/or lead physical implementation of high-performance integrated circuits for TeraWave, its satellite communications network. The role works closely with circuit designers on layouts for high-speed data converters (ADCs/DACs), PLLs, filters, amplifiers, clocking, and biasing circuits. The designer delivers high-quality, manufacturable layouts that meet performance, reliability, and integration requirements. Responsibilities and technical leadership scope vary according to experience and level. The position is based on site in San Diego, California (preferred), or Cupertino, California. A temporary remote-work exception is approved while the San Diego site is being developed. Relocation is provided, travel is expected up to 10% of the time, and interviews include a technical assessment.

Requirements

Bachelor’s degree in electrical engineering.
10 or more years of relevant professional experience.
Understanding of basic electrical parameters and relationships, including Ohm’s law and calculations for sizing metal layers to meet IR-drop and current-density requirements.
Direct hands-on experience developing analog/mixed-signal custom layouts in FinFET technologies.
Strong understanding of device matching, symmetry, parasitic effects, noise isolation, coloring, and layout-dependent effects.
Proficiency with Cadence Virtuoso, including connectivity-driven layout using Virtuoso XL.
Experience with Siemens Calibre or equivalent physical verification tools, including DRC/LVS debugging.
Understanding of advanced-node layout constraints, electromigration, current density, and power-routing requirements.
Experience translating circuit schematics and designer requirements into verified device- and block-level layouts.
Strong communication skills and ability to work independently on challenging layout problems.
Must be a U.S. citizen or national, U.S. permanent resident (current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.

Nice To Haves

Experience with high-speed ADC/DAC, amplifier, filter, PLL, clock-distribution, reference-generator, and LDO layouts.
Experience with full-chip floorplanning, hierarchical integration, and successful tape-out delivery.
Experience preparing and releasing final layout databases to the foundry.
Familiarity with chip-level ESD structures, pad integration, density fill, and design-for-manufacturability requirements.
Experience resolving complex physical-verification issues across hierarchical designs.
Experience leading layout projects, coordinating multiple contributors, and mentoring layout designers.
Experience collaborating with packaging engineers on pad placement and die interfaces.

Responsibilities

Develop custom transistor-level layouts for analog/mixed-signal circuits in advanced FinFET technologies, including floorplanning, top-level integration, device placement, routing, and physical verification.
Collaborate with circuit designers to meet performance, matching, noise-isolation, area, and reliability requirements.
Apply FinFET-specific layout techniques to address device geometry constraints, orientation, layout-dependent effects, and parasitic coupling.
Implement matched device structures, sensitive signal routing, shielding, and isolation appropriate to circuit requirements.
Perform design rule checking (DRC), electrical rule checking (ERC), and layout-versus-schematic (LVS) verification; investigate and resolve complex verification errors.
Generate parasitic extraction results and collaborate with circuit designers to identify and resolve layout-related performance issues.
Implement power and ground distribution that meets electromigration, current-density, and voltage-drop requirements.
Develop layout schedules, identify implementation risks and dependencies, and deliver verified layouts in alignment with project milestones.
Support hierarchical planning, top-level integration, and tape-out preparation, including ESD structures, pad integration, density fill, and applicable design-for-manufacturability checks.
Collaborate with circuit designers, CAD engineers, and foundry partners to resolve layout, PDK, and verification issues.
Lead layout reviews, document best practices, and mentor less-experienced layout designers.

Benefits

Medical insurance.
Dental insurance.
Vision insurance.
Basic and supplemental life insurance.
Paid parental leave.
Short- and long-term disability.
401(k) with a company match of up to 5%.
Education Support Program.
Stock options for regular employees working at least 20 hours per week.
Paid time off of up to four weeks per year based on weekly scheduled hours.
Up to 14 company-paid holidays.
Depending on role type and job level, employees may be eligible for benefits and bonuses based on individual contributions and company results or other factors.