Layout/Mask Design

Apple • Austin, TX

18h • Onsite

About The Position

APPLE INC is hiring for a position in Austin, Texas. The role designs complex custom layouts for digital circuits in deep SubMicron CMOS technologies. The employee works with layout leads and circuit designers to review and analyze floorplans, run layout design verification tools, and clean up megacells to meet engineering specifications. The role also helps plan and schedule work, negotiate layout tradeoffs, interpret verification reports, and use advanced CAD tools and mask design knowledge to make layout corrections and create robust physical representations of circuits. The position uses advanced layout techniques to achieve best-in-class power, performance, and area (PPA) for critical designs; reviews EMIR simulations and applies fixes for robust power delivery; and uses automated place-and-route tools to accelerate digital layout execution. The schedule is 40 hours per week.

Requirements

• Bachelor's degree or foreign equivalent in Electrical Engineering or a related field.
• At least 2 years of experience in the job offered or a related occupation.
• Experience or education using layout floor-planning, standard cell planning, and hierarchical layout assembly to generate layouts optimized for power, performance, and area.
• Experience or education resolving issues involving RC delay, electromigration, self-heating, and cross capacitance.
• Ability to recognize failure-prone layout structures and work with designers on solutions, including shielding critical signals, analyzing DFM yields, and addressing LOD effects.
• Experience or education creating layouts with a robust PG grid using IR simulation tools.
• Ability to collaborate and communicate effectively with multifunctional teams to understand engineering specifications and meet delivery timelines.
• Experience or education interpreting CALIBRE DRC, ERC, LVS, and DFM reports to complete layouts.
• Experience or education using CADENCE Virtuoso layout design tools to draw layouts and increase productivity.

Responsibilities

• Design complex custom layouts for digital circuits in deep SubMicron CMOS technologies.
• Work with layout leads and circuit designers to review and analyze circuit floorplans.
• Run a complete set of available layout design verification tools and clean up megacells to match engineering specifications.
• Work with the layout lead and circuit design team to plan and schedule work and negotiate layout tradeoffs.
• Interpret LVS, DRC, and ERC reports to determine an efficient path to completing layouts.
• Use advanced CAD tools and mask design knowledge to make layout corrections and create robust physical design representations of circuits.
• Apply advanced layout techniques to achieve best-in-class PPA for critical designs.
• Review EMIR simulations with the design lead and apply necessary fixes for robust power delivery.
• Use automated place-and-route tools to speed up layout execution for digital designs.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level