Layout/Mask Designer

Micron Technology • Boise, ID

2d

About The Position

Create physical layouts of transistors, resistors, and capacitors for analog circuits used in memory product development. Develop layouts that meet process rules and match the schematic, including floor planning, routing, and power bus design. Support the team in establishing IP layout work modes, including layout standardization, co-work flows, and alignment methods to minimize impact. Deliver quality layouts on time, monitor layout quality, pass SPF, confirm results with circuit designers, and deliver layout and DBR on time.

Provide IC layout design support through floor planning, custom layout, analog/mixed-signal layout, and full-chip-level layout design. Perform layout verification, including LVS, DRC, and DFM; provide support, quality checks, and documentation. Complete function blocks with good layout quality under broad instructions, apply judgment when interpreting results and conducting quantitative analysis, and communicate with engineering teams in India, Japan, and the US to help ensure project success.

Requirements

• Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Knowledge of DRAM circuit functions.
• Experience with IC custom layout for IP layout design.
• Experience with Cadence OA and Caliber verification tools.
• Knowledge of design rule check (DRC) and layout versus schematic (LVS).
• Experience making layout patterns.
• Knowledge of industrial applications of devices and sensors.

Responsibilities

• Create physical layouts of transistors, resistors, and capacitors for analog circuits used in memory product development.
• Ensure layouts meet process rules and match schematics.
• Perform floor planning, routing, and power bus design.
• Support establishment of IP layout work modes, including layout standardization, co-work flows, and alignment methods to minimize impact.
• Deliver quality layouts on time, monitor layout quality, pass SPF, confirm results with circuit designers, and deliver layout and DBR on time.
• Provide IC layout design support for floor planning, custom layout, analog/mixed-signal layout, and full-chip-level layout designs.
• Perform layout verification, including LVS, DRC, and DFM, and provide support, quality checks, and documentation.
• Complete function blocks with good layout quality under broad instructions.
• Interpret results, conduct quantitative analysis, and exercise judgment.
• Communicate with engineering teams in India, Japan, and the US to support project success.

Benefits

• Choice of medical, dental, and vision plans.
• Programs to help protect income in case of illness or injury.
• Paid family leave.
• Paid time off program.
• Paid holidays.

What This Job Offers

• Job Type: Full-time