Layout/Mask Designer

Apple•Beaverton, OR

About The Position

Apple Inc. has an available Layout/Mask Designer position in Beaverton, Oregon. The role designs complex custom layouts for digital circuits in deep submicron CMOS technologies and works with circuit designers to review and analyze floorplans and complex circuits. It uses advanced CAD and mask-design knowledge to correct layouts and create robust physical representations of circuits, while applying advanced layout techniques to achieve strong PPA for critical designs. The designer runs layout design verification tools on completed megacells, analyzes LVS, DRC, and ERC reports, performs EMIR simulations and applies fixes for robust power delivery, and uses automated P&R tools to accelerate digital layout execution. The role also plans and schedules work with the circuit design team, negotiates layout tradeoffs, and reviews peers’ layouts to recommend improvements. The position is 40 hours per week.

Requirements

Master’s degree or foreign equivalent in Electrical Engineering, Computer Engineering, Electronics Engineering, or a related field.
Two years of experience in the job offered or a related occupation.
Two years of experience using knowledge of layout floor-planning, standard-cell planning, and hierarchical layout assembly.
Two years of experience applying understanding of RC delay, electromigration, self-heating, and cross-capacitance issues to perform optimal wire planning.
Two years of experience recognizing layout structures prone to failure and collaborating with other designers to identify solutions.
Two years of experience designing and validating a robust power grid using IR simulation tools to avoid failure-prone networks.
Two years of experience interpreting DRC and LVS reports to build manufacturable layouts.
Two years of experience using Cadence Virtuoso layout-design tools to design layout structures.
Two years of experience using circuit and layout knowledge to create low-noise, low-power data paths and/or memory layout structures.

Responsibilities

Design complex custom layouts for digital circuits in deep submicron CMOS technologies.
Review and analyze floorplans and complex circuits with circuit designers.
Run the available layout design verification tools on completed megacells.
Work with the circuit design team to plan and schedule work and negotiate layout tradeoffs.
Analyze LVS, DRC, and ERC reports to identify an efficient path to completing layouts.
Use advanced CAD tools and mask-design knowledge to correct layouts and produce robust physical circuit representations.
Apply advanced layout techniques to achieve best-in-class PPA for critical designs.
Perform EMIR simulations and apply fixes to achieve robust power delivery.
Review layouts designed by peers and provide improvement recommendations.
Use automated P&R tools to speed up digital layout execution.