IC Design Engineer (STA/ Synthesis)

Broadcom • San Jose, CA

8d

About The Position

Broadcom is seeking a lead STA/Synthesis engineer to contribute to constraint development and validation, synthesis, static audits, and timing closure for mission-critical IP and ASIC blocks in advanced technology nodes. The role covers complex SoC designs and high-speed digital and mixed-signal blocks, with responsibilities spanning timing analysis, signoff methodology, quality-of-results analysis, process automation, and timing ECOs. The engineer will also provide guidance on clock tree synthesis and optimization and ensure compliance with timing signoff criteria.

Requirements

• Experience with high-complexity silicon in advanced technology nodes.
• Familiarity with timing constraint development for hierarchical designs.
• Knowledge of clock tree planning and implementation for SoCs.
• Experience with timing ECO creation and final timing signoff.
• Proficiency with STA tools such as PrimeTime, TCM, and Tempus, and scripting languages such as Tcl and Perl.
• Proficiency with synthesis and audit tools such as DC-T, Genus, Fishtail, VCLP, and Formality.
• Strong understanding of ASIC design flows, including RTL and place-and-route.
• Excellent problem-solving skills and attention to detail.
• Effective communication and teamwork abilities.
• Ability to work independently in a fast-paced, cross-geographical environment.
• At least a bachelor's degree and 12+ years of related experience, a master's degree and 10+ years of related experience, or a PhD and 7+ years of related experience.
• At this level, post-graduate coursework is highly desirable.

Nice To Haves

• Direct or indirect experience with RTL/design.
• Post-graduate coursework is highly desirable.

Responsibilities

• Develop and validate timing constraints for intricate SoC designs.
• Perform static timing analysis (STA) using industry-standard tools such as PrimeTime and Tempus.
• Perform synthesis and static audits, including CDC, RDC, low-power, and equivalence checks, for high-speed, complex digital and mixed-signal blocks.
• Define and implement timing signoff methodologies, including process corners, derates, and uncertainties.
• Conduct pre-route timing checks and quality-of-results (QoR) analysis.
• Automate timing analysis processes using scripting languages such as Tcl or Perl.
• Provide guidance on clock tree synthesis and optimization for energy-efficient designs.
• Ensure compliance with timing signoff checklists and criteria.
• Generate timing ECOs for timing closure.
• Drive timing closure for complex IP and ASIC blocks.

Benefits

• Discretionary annual bonus.
• Competitive new-hire equity grant and annual equity awards, subject to applicable plan documents and award agreements.
• Medical, dental, and vision plans.
• 401(k) participation with company matching.
• Employee Stock Purchase Program (ESPP).
• Employee Assistance Program (EAP).
• Company-paid holidays.
• Paid sick leave and vacation time.
• Paid Family Leave and other leaves of absence in accordance with applicable laws.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior