Synthesis & STA Engineer – High-Speed SerDes

Astera Labs•San Jose, CA

11d

About The Position

Astera Labs is hiring a Synthesis & STA Engineer to support the design of high-speed analog/mixed-signal SerDes and connectivity ASICs. The position owns logic synthesis and static timing analysis across the digital portions of mixed-signal SerDes PHY designs, collaborating with analog, RTL, physical design, and verification teams to achieve robust timing closure at advanced process nodes. The role involves synthesis and optimization of digital controller and DSP blocks; development and validation of timing constraints; management of multi-mode, multi-corner analysis; and timing closure from synthesis through sign-off. It also supports hierarchical timing analysis, timing debug and ECOs, and integration of SerDes IP at block and full-chip levels. The engineer will contribute timing and interface budgets, clock and power-domain strategies, and automation to improve STA turnaround time. The salary range is $160,000–$200,000. Actual compensation depends on experience, level, location, and business need. The role may also be eligible for discretionary bonuses, equity incentives, and comprehensive benefits.

Requirements

Bachelor's degree in Electrical Engineering or Computer Science.
At least 8 years of experience in synthesis, timing-constraint development, STA, and sign-off for high-speed mixed-signal IP in server, storage, networking, or SerDes applications.
Strong proficiency in writing and debugging SDC constraints, with deep understanding of clock modeling, generated clocks, clock-domain crossings, and exception handling.
Expertise in STA methodology and timing closure at block and full-chip levels using Synopsys PrimeTime and/or Cadence Tempus.
Strong knowledge of synthesis, place-and-route, extraction, and equivalence-checking flows such as Formality or Conformal in advanced nodes (5nm/3nm and below).
Proficiency with Cadence and/or Synopsys physical-design and STA toolchains.
Scripting ability in Tcl, Python, and/or Perl.
Ability to work independently, prioritize effectively, and maintain a professional, customer-focused mindset.

Nice To Haves

Master's degree.
Direct experience with high-speed SerDes, Ethernet PHY (112G/224G), or PCIe/CXL PHY digital-controller and DSP timing challenges.
Understanding of analog/mixed-signal integration, including analog-digital interface timing, PLL/DLL/CDR clock structures, and level-shifter/isolation-cell constraints.
Knowledge of ECO methodologies, DFT tools, and test-coverage analysis for mixed-signal designs.
Experience working with IP vendors on RTL and hard-macro integration, including Liberty (.lib), LEF, and behavioral-model characterization.
SystemVerilog/Verilog proficiency.
Familiarity with power-aware synthesis and STA (UPF/CPF flows).
Experience with high-speed clocking architectures and multi-rate clock-domain management typical of SerDes designs.

Responsibilities

Perform RTL synthesis and optimize area, power, and timing for digital controller and DSP blocks in high-speed SerDes PHY designs.
Author, develop, and validate SDC constraints, including clock definitions, generated clocks, multi-frequency and multi-mode constraints, I/O delays, false paths, multicycle paths, and clock-domain crossing exceptions.
Set up and manage MMMC environments for STA across process, voltage, and temperature corners.
Drive timing closure from synthesis through sign-off for digital blocks in mixed-signal SerDes IP and full-chip SoC integration.
Define and manage I/O timing budgets and interface constraints at analog-digital boundaries in hierarchical mixed-signal designs.
Apply advanced sign-off methodologies at TSMC 5nm/3nm and below, including OCV/AOCV/POCV and relevant PVT effects.
Use ETM/ILM libraries for hierarchical timing analysis and correlation of SerDes hard-macro blocks, balancing runtime and accuracy.
Provide timing feedback, root-cause analysis, timing debug, and ECO guidance at block and full-chip levels.
Manage large-scale multi-corner, multi-mode STA runs through automation, partitioning, and efficient resource use; develop scripts and flows to improve turnaround time.
Generate and validate timing ECOs in partnership with physical design, analog, and RTL teams.
Collaborate with analog/mixed-signal, SerDes architecture, implementation, and verification teams to drive timing convergence and provide sign-off expertise for PHY-level and chip-level integration.
Collaborate on clock-tree and power-domain strategies for SerDes digital blocks, including compatibility with PLL/CDR-generated clocks and multi-supply domains.