IC Design Engineer (STA/ Synthesis)
About The Position
Broadcom is seeking a lead STA/Synthesis engineer to contribute to constraint development and validation, synthesis, static audits, and timing closure for mission-critical IP and ASIC blocks in advanced technology nodes. The role focuses on complex SoC designs, high-speed digital and mixed-signal blocks, and timing signoff methodologies. The engineer will use industry-standard timing, synthesis, and audit tools and automate analysis processes with scripting languages. The position requires at least a bachelor's degree and 12+ years of related experience, a master's degree and 10+ years of related experience, or a Ph.D. and 7+ years of related experience. Post-graduate coursework is highly desirable at this level. Direct or indirect RTL/design experience is a plus. The annual base salary range is USD 143,800 to USD 230,000. Eligible compensation also includes a discretionary annual bonus and the opportunity for new-hire and annual equity awards, subject to applicable plan documents and award agreements. Broadcom offers medical, dental, and vision plans; 401(k) participation with company matching; an Employee Stock Purchase Program; an Employee Assistance Program; company-paid holidays; paid sick leave and vacation time; and leave in accordance with applicable laws.
Requirements
- Experience with high-complexity silicon in advanced technology nodes.
- Familiarity with timing constraint development for hierarchical designs.
- Knowledge of clock tree planning and implementation for SoCs.
- Experience with timing ECO creation and final timing signoff.
- Proficiency with STA tools such as PrimeTime, TCM, or Tempus and scripting languages such as Tcl or Perl.
- Proficiency with synthesis and audit tools such as DC-T, Genus, Fishtail, VCLP, and Formality.
- Strong understanding of ASIC design flows, including RTL and place-and-route.
- Excellent problem-solving skills and attention to detail.
- Effective communication and teamwork abilities.
- Ability to work independently in a fast-paced, cross-geographical environment.
- At least a bachelor's degree and 12+ years of related experience, a master's degree and 10+ years of related experience, or a Ph.D. and 7+ years of related experience.
Nice To Haves
- Post-graduate coursework is highly desirable.
- Direct or indirect experience with RTL/design is a plus.
Responsibilities
- Develop and validate timing constraints for intricate SoC designs.
- Perform static timing analysis using industry-standard tools such as PrimeTime and Tempus.
- Perform synthesis and static audits, including CDC, RDC, low-power, and equivalence audits, for high-speed, complex digital and mixed-signal blocks.
- Define and implement timing signoff methodologies, including process corners, derates, and uncertainties.
- Conduct pre-route timing checks and quality-of-results analysis.
- Automate timing analysis processes using scripting languages such as Tcl or Perl.
- Provide guidance on clock tree synthesis and optimization for energy-efficient designs.
- Ensure compliance with timing signoff checklists and criteria.
- Generate timing ECOs for timing closure.
- Drive timing closure for complex IP and ASIC blocks.
Benefits
- Discretionary annual bonus eligibility.
- Opportunity to receive a competitive new-hire equity grant and annual equity awards.
- Medical, dental, and vision plans.
- 401(k) participation with company matching.
- Employee Stock Purchase Program (ESPP).
- Employee Assistance Program (EAP).
- Company-paid holidays.
- Paid sick leave and vacation time.
- Paid Family Leave and other leaves of absence in accordance with applicable laws.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
