STA Engineer

Apple • Cupertino, CA

2d

About The Position

As an ASIC STA Engineer, you will work on various aspects of SoC timing, owning full-chip and block-level timing closure and constraints throughout the project. You will collaborate with SoC Design, SoC Design Verification, DFT, Architecture, and Physical Design teams, as well as CAD and Flow teams, to define and improve front-end design methodologies. You will develop and maintain methodologies and flows related to timing analysis and support leading-edge IP development and integration across multiple SoC teams.

Requirements

• Bachelor’s degree.
• Strong fundamentals in digital design.
• Familiarity with ASIC design timing concepts.
• Proficiency in scripting languages such as TCL, Python, and Perl.
• Self-starter and highly motivated.
• Ability to communicate effectively across internal groups.

Nice To Haves

• Exposure to STA tools such as PrimeTime.
• Experience writing timing constraints and knowledge of timing corners and modes.
• Familiarity with front-end tools and methodologies such as synthesis and logic equivalence checks.

Responsibilities

• Own full-chip and block-level timing closure and constraints throughout the project.
• Collaborate with SoC Design, SoC Design Verification, DFT, Architecture, and Physical Design teams.
• Work with CAD and Flow teams to define and improve front-end design methodologies.
• Develop and maintain methodologies and flows related to timing analysis.
• Coordinate design and integration tasks with multiple SoC teams to support high-quality IP deliverables.

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level