Senior | Principal Foundry Interface Design Engineer - HBM- TPG

Micron•Folsom, CA

13h•Onsite

About The Position

The HBM Design Architecture team within Micron’s HBM DRAM Engineering Group works at the intersection of design, technology, and manufacturing to deliver next-generation HBM solutions. In this full-time, onsite role, the engineer provides technology support for the design and development of advanced HBM DRAM products, serving as a bridge between internal design teams, foundries, and technology development groups. The role translates advanced process capabilities into scalable, high-performance architectures and contributes to performance, power efficiency, reliability, and the long-term HBM roadmap. It also supports the design and deployment of AI-enabled solutions to improve efficiency and decision-making. Responsibilities are grouped into five focus areas: Foundry Interface and Technology Alignment; Circuit Simulation and Analysis; Test-Chip and Silicon Validation; PDK and Design Enablement; and AI-Enabled Productivity and Efficiency Improvement. Candidates are expected to have proven experience in at least three of these areas.

Requirements

Bachelor’s, master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience.
At least 5 years of semiconductor industry experience.
Solid understanding of advanced semiconductor technology development.
Strong grasp of advanced CMOS technology nodes, FinFET devices, and process integration.
Hands-on experience with HSPICE simulations, device characterization, standard cell benchmarking, PPA analysis, and parasitic extraction and physical verification.
Proven experience in at least three of the five focus areas listed in the job description.

Nice To Haves

Experience working directly with leading foundries such as TSMC, Samsung, Intel Foundry Services, or GlobalFoundries.
Experience with memory products, including DRAM, HBM, or SRAM.
Knowledge of TSV technologies, advanced packaging, reliability modeling and aging simulations, advanced BEOL technologies, and PDK development and validation.
Ability to use AI tools to summarize, analyze, and extract insights from PDK documentation, Design Rule Manuals, reliability reports, foundry collateral, and silicon characterization data.
Experience leading technology pathfinding and node selection activities.

Responsibilities

Support the design and development of advanced HBM DRAM products.
Bridge internal design teams, foundries, and technology development groups.
Translate advanced process capabilities into scalable, high-performance architectures.
Contribute to performance, power efficiency, reliability, and long-term HBM roadmap success.
Work in one or more of the focus areas: foundry interface and technology alignment; circuit simulation and analysis; test-chip and silicon validation; PDK and design enablement; and AI-enabled productivity and efficiency improvement.
Drive AI-enabled engineering practices and automation to improve the efficiency of DTCO analysis, foundry collateral evaluation, PDK enablement, benchmarking, and collaboration across build teams.