Principal Foundry Interface Design Engineer, HBM

Micron•Folsom, CA

1d•Onsite

About The Position

Micron’s HBM Design Architecture team works at the intersection of design, technology, and manufacturing to deliver next-generation HBM solutions for AI and machine-learning workloads. In this full-time, onsite role, the engineer provides technology support for the design and development of advanced HBM DRAM products, serving as a bridge between internal design teams, foundries, and technology development groups. The role translates advanced process capabilities into scalable, high-performance architectures that affect performance, power efficiency, reliability, and the long-term HBM roadmap. The position also supports the design and deployment of AI-enabled solutions that improve efficiency and decision-making. Candidates are expected to demonstrate proven experience in at least three of five focus areas: foundry interface and technology alignment; circuit simulation and analysis; test-chip and silicon validation; PDK and design enablement; and AI-enabled productivity and efficiency improvement. The role may involve engaging foundry partners and internal teams, evaluating process and design collateral, conducting simulations and silicon analysis, and developing design guidelines and automation practices.

Requirements

BS, MS, PhD, or equivalent experience in Electrical Engineering, Computer Engineering, or a related field.
At least 5 years of semiconductor industry experience.
Solid understanding of advanced semiconductor technology development.
Strong grasp of advanced CMOS technology nodes, FinFET devices, and process integration.
Hands-on experience with HSPICE simulations, device characterization, standard cell benchmarking, PPA analysis, parasitic extraction, and physical verification.
Experience driving AI-enabled engineering practices and automation to improve the efficiency of DTCO analysis, foundry collateral evaluation, PDK enablement, benchmarking, and collaboration across build teams.

Nice To Haves

Experience working directly with leading foundries such as TSMC, Samsung, Intel Foundry Services, or GlobalFoundries.
Experience with memory products including DRAM, HBM, or SRAM.
Knowledge of TSV technologies, advanced packaging, reliability modeling and aging simulations, advanced BEOL technologies, and PDK development and validation.
Ability to apply AI tools to summarize, analyze, and extract insights from PDK documentation, Design Rule Manuals (DRMs), reliability reports, foundry collateral, and silicon characterization data.
Experience leading technology pathfinding and node selection activities.

Responsibilities

Act as the primary technical interface between foundry partners and Micron design organizations.
Drive closure of design-process gaps through collaboration with foundry process teams.
Influence foundry roadmaps related to TSV, BEOL, reliability, and design enablement.
Define technology requirements for future HBM and custom memory products.
Perform HSPICE simulations for technology evaluation and design optimization.
Evaluate compact models, PDK SPICE models, and process corners.
Conduct pre-layout and post-layout circuit analysis.
Support BEOL optimization and routing studies through simulation.
Develop methodologies for evaluating design sensitivity to process variations.
Plan and implement technology evaluation test chips.
Define process monitor structures and benchmark vehicles.
Analyze post-silicon data and correlate results with simulations.
Collaborate with product engineering and foundry/Fab teams on silicon learning and technology qualification.
Evaluate foundry PDKs and IP collateral.
Provide design teams with technology guidelines and best-known methods.
Drive creation of design recommendations, analog guidelines, and digital PPA evaluation methodologies.
Collaborate with CAD teams on flow enablement and validation.
Identify and implement AI-enabled workflows, automation opportunities, and knowledge-management practices to improve engineering productivity, decision quality, and execution efficiency across DTCO, foundry interface, PDK evaluation, and design enablement activities.