Principal Foundry Interface Design Engineer, HBM

Micron Technology•Folsom, CA
•$150,000 - $308,000•Onsite

About The Position

The Principal Foundry Interface Design Engineer will join Micron’s HBM Design Architecture team within the HBM DRAM Engineering Group. The team works across design, technology, and manufacturing to develop next-generation HBM solutions for AI and machine-learning workloads. In this full-time, onsite role, the engineer provides technology support for the design and development of advanced HBM DRAM products. The role bridges internal design teams, foundries, and technology development groups, translating advanced process capabilities into scalable, high-performance architectures. The work contributes to product performance, power efficiency, reliability, and long-term HBM roadmap success, and supports AI-enabled solutions that improve efficiency and decision-making. Candidates are expected to demonstrate proven experience in at least three of the five focus areas: foundry interface and technology alignment; circuit simulation and analysis; test-chip and silicon validation; PDK and design enablement; and AI-enabled productivity and efficiency improvement.

Requirements

  • BS, MS, PhD, or equivalent experience in Electrical Engineering, Computer Engineering, or a related field.
  • At least 5 years of semiconductor industry experience.
  • Solid understanding of advanced semiconductor technology development.
  • Strong grasp of advanced CMOS technology nodes, FinFET devices, and process integration.
  • Hands-on experience with HSPICE simulations, device characterization, standard-cell benchmarking, PPA analysis, parasitic extraction, and physical verification.
  • Experience driving AI-enabled engineering practices and automation to improve DTCO analysis, foundry collateral evaluation, PDK enablement, benchmarking, and collaboration across build teams.
  • Proven experience in at least three of the five stated focus areas.

Nice To Haves

  • Experience working directly with leading foundries such as TSMC, Samsung, Intel Foundry Services, or GlobalFoundries.
  • Experience with memory products, including DRAM, HBM, or SRAM.
  • Knowledge of TSV technologies, advanced packaging, reliability modeling and aging simulations, advanced BEOL technologies, and PDK development and validation.
  • Ability to use AI tools to summarize, analyze, and extract insights from PDK documentation, Design Rule Manuals (DRMs), reliability reports, foundry collateral, and silicon characterization data.
  • Experience leading technology pathfinding and node-selection activities.

Responsibilities

  • Provide technology support for the design and development of advanced HBM DRAM products.
  • Serve as a bridge between internal design teams, foundries, and technology development groups.
  • Translate advanced process capabilities into scalable, high-performance architectures.
  • Contribute to performance, power efficiency, reliability, and long-term HBM roadmap success.
  • Support design and deployment of AI-enabled solutions that improve efficiency and decision-making.
  • Work in focus areas that include foundry interface and technology alignment, circuit simulation and analysis, test-chip and silicon validation, PDK and design enablement, and AI-enabled productivity and efficiency improvement.

Benefits

  • Medical, dental, and vision plans.
  • Programs that help protect income if unable to work due to illness or injury.
  • Paid family leave.
  • Paid time off.
  • Paid holidays.
  • Additional compensation may include bonuses and equity.
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