Copy of Copy of Director, Package Design Engineering

Renesas Electronics•Austin, TX

8h•Onsite

About The Position

This role focuses on Package Technology Development/NPI, R&D, and Global OSAT management for new Package Development/Product qualification. It involves Technology Roadmap definition, R&D budget management, and customer adoption programs. The primary focus is on the design and development of package and interconnect methods for Renesas’s AI/Datacenter Infrastructure Power packaging needs, specifically Smart Power Stages, Vertical Power Stages, Power Modules & Discrete FET packages. The scope also includes WBG (SiC & GaN) development, DBC, AMB substrates, and advanced interconnect technologies. Knowledge of wafer level, flip-chip, multi-chip module, and power devices is considered a plus. The position requires benchmarking, selection, and qualification of suitable materials, processes, and assembly subcontractors (OSAT) or contract manufacturers (CM). The role involves working with OSAT/CM to develop and run Design of Experiments (DOE) to optimize processes and establish process specifications. Collaboration with Product groups and the Reliability team is essential for qualifying new packages and processes within the required timeframe. The individual will be responsible for resolving process integration issues, ensuring all window checks are performed on critical process steps, and establishing production controls and monitors to prevent quality incidents. A smooth transition into production and implementation of ramp-up monitors are key. The role also entails working with OSAT/CM to monitor and resolve process issues early in the production phase to ensure high-quality parts are shipped to customers. Developing and maintaining technical expertise on advances and innovations in power SiP/modules, wafer level packaging & flip chip interconnects is crucial. Participation in packaging roadmap development with a focus on execution is expected. The position requires addressing internal and external customer complaints in collaboration with peers from Marketing, Product groups, Quality, and Operations organizations to support business growth. Establishing and maintaining package design rules is also a responsibility.

Requirements

Doctorate/Masters / Bachelor’s Degree in Physics, Chemistry, Mechanical, Electrical or Materials Engineering.
15 to 20 years of relevant experience in package development emphasizing power SiP/module, wafer level & flip-chip packaging
Strong understanding of power SiP/modules, wafer level/flip-chip packaging methods, assembly process knowledge, qualification methods, SPC and statistical analysis software
Knowledge of wire-bonding & multi-chip module technologies a plus.
Strong interpersonal and communication skills.
Strong analytical and presentation skills.

Nice To Haves

Knowledge of wafer level, flip-chip, multi-chip module and power devices will be a plus.
Knowledge of wire-bonding & multi-chip module technologies a plus.

Responsibilities

Package Technology Development/NPI, R&D, Global OSAT management for new Package Development/Product qualification, Technology Roadmap definition, R&D budget management & customer adoption programs.
Focus on design and development of package and interconnect methods for Renesas’s AI/Datacenter Infrastructure Power packaging needs especially Smart Power Stages, Vertical Power Stages, Power Modules & Discrete FET packages. Scope also involves WBG (Ie. SiC & GaN) development along with DBC, AMB substrates and advanced interconnect technologies. Knowledge of wafer level, flip-chip, multi-chip module and power devices will be a plus.
Benchmark, select and qualify suitable materials, processes and assembly subcontractors (OSAT) or contract manufacturers (CM).
Work with OSAT/CM to develop, run DOE to optimize processes and establish process spec.
Work with Product groups and Reliability team, qualify new packages and processes within required time frame.
Resolve all process integration issues by ensuring all window checks are done on critical process steps.
Establish production controls and monitors to ensure there is no room for quality incidents.
Ensure smooth transition into production & implement ramp up monitor.
Work with OSAT/CM to monitor and resolve process issues early in the production phase to ensure only parts with superior quality shipped to customer.
Develop and maintain technical expertise on advances and innovations in power SiP/modules, wafer level packaging & flip chip interconnects.
Participate in packaging roadmap development & focus on execution.
Address internal and external customer complaints working with peers of Marketing, Product groups, Quality and Operations organization to satisfy growth in businesses.
Establish & maintain package design rules.