Design Verification Engineer

Broadcom•Broomfield, CO

About The Position

Broadcom's ASIC Products Division (APD), a worldwide leader in the design of complex custom ASICs and embedded IP, is looking for an experienced verification engineer that will be responsible for modeling and verification activities related to complex digital and mixed signal (MXS) IP blocks used in Broadcom’s ASIC developments. The engineer will be responsible for defining verification plans and environment architecture, developing test cases and test bench components, coverage analysis and closure, and debug. This position may involve working with emulation and FPGA prototyping platforms and leading efforts in evaluating and driving the adoption of advanced verification methodologies/flows. The engineer will be expected to develop functional models to facilitate the block, system, and ASIC level verification. The candidate must work closely with the design teams and EDA vendors to accomplish the modeling and verification tasks. The candidate must have experience using SystemVerilog and UVM, designing verification components including UVM agents, checkers, and behavioral models. Experience with implementing and achieving coverage goals by developing random & directed test cases, and SystemVerilog Assertions. This engineer will be responsible for analyzing and debugging simulation failures at the RTL and gate-level. The engineer must be knowledgeable of RTL, gate-level netlists, and SDF and capable of analyzing such formats in the verification context.

Requirements

6+ years of experience with verification concepts and architectures for complex digital and MXS circuits
Experience verifying designs at the block and system levels
Experience with complex digital and mixed-signal circuits (PLL, DLL, ADC, DAC)
Experience debugging RTL and gate-level netlists, analyzing schematic diagrams of analog / MXS circuits
Experience using SystemVerilog and advanced verification concepts and methodologies (UVM, SVA)
Experience with Synopsys, Cadence, and Mentor simulations tools
Demonstrated ability to plan and deploy complex, reusable, and scalable verification environments
Experience with Perl/Python and Tcl or other scripting languages
Experience with version control systems (DesignSync, git)
Superior writing, grammar, and verbal communication skills
Excellent problem solver; develops and employs automated processes where applicable
Worked independently and in a global team and dynamic environment in a highly visible role
Possesses ability to learn and adapt to new tools and methodologies on the fly
Must have legal authorization to work in the US

Nice To Haves

Experience with hardware design and debug
Experience with emulation (Palladium, Veloce, Zebu) and FPGA (Xilinx) platforms
Formal verification concepts / experience is a plus
Experience with verifying iJTAG network using ICL and PDL in the Tessent tool a plus
Experience with co-simulation a plus

Responsibilities

Defining verification plans and environment architecture
Developing test cases and test bench components
Coverage analysis and closure
Debug
Working with emulation and FPGA prototyping platforms
Evaluating and driving the adoption of advanced verification methodologies/flows
Developing functional models to facilitate block, system, and ASIC level verification
Working closely with design teams and EDA vendors
Designing verification components including UVM agents, checkers, and behavioral models
Implementing and achieving coverage goals by developing random & directed test cases, and SystemVerilog Assertions
Analyzing and debugging simulation failures at the RTL and gate-level
Analyzing RTL, gate-level netlists, and SDF in the verification context