Design Verification Engineer

Apple • Beaverton, OR

4h

About The Position

At Apple, we work every single day to craft products that enrich people’s lives. This opportunity is for an outstandingly hardworking design verification engineer to join a wide-ranging group and craft upcoming products that will delight and inspire millions of Apple’s customers daily. This role focuses on enabling the production of fully functional first silicon for IP designs. Responsibilities encompass all phases of pre-silicon verification, including establishing DV methodology, test-plan development, verification environment development (stimulus and checkers), test-writing, debug, coverage, and sign-off for RTL freeze and tape-out. The engineer will be responsible for ensuring bug-free first silicon for parts of the SoC/IP, developing detailed test and coverage plans based on micro-architecture, and creating scalable and portable verification environments. This includes developing all verification environment components like stimulus, checkers, assertions, trackers, and coverage. A mindset to break the design is highly desirable. The role also involves developing and implementing verification plans, including design and DV environment bring-up, regression enabling, and debugging test failures. The engineer will develop block, IP, and SoC level test-benches, track and report DV progress using metrics, and utilize LLM and related technologies for efficient execution and improved quality.

Requirements

• Bachelors degree

Nice To Haves

• BS degree in technical subject area with minimum 3 years of proven experience or equivalent
• Strong knowledge of OOP, SystemVerilog and UVM
• Strong knowledge in developing scalable and portable test-benches
• Proven experience with verification methodologies and tools such as simulators, waveform viewer, build and run automation, coverage collection, gate level simulations
• Some working experience using LLMs for efficiency and quality
• Experience with power-aware (UPF) or similar verification methodology
• Knowledge of one of the scripting languages such as Python, Perl, TCL
• Some experience with serial protocols such as PCIe or USB, parallel protocol such as DDR
• Knowledge of formal verification methodology
• Knowledge of emulation for verification technologies

Responsibilities

• Establish DV methodology
• Develop test-plans
• Develop verification environment, including stimulus and checkers
• Perform test-writing
• Debug issues
• Manage coverage
• Perform sign-off for RTL freeze and tape-out
• Ensure bug-free first silicon for part of the SoC / IP
• Develop detailed test and coverage plans based on the micro-architecture
• Develop verification methodology suitable for the IP, ensuring a scalable and portable environment
• Develop verification environment, including all respective components such as stimulus, checkers, assertions, trackers, coverage
• Develop verification plans for all features under care
• Implement verification plans, including design bring-up, DV environment bring-up, regression enabling all features under care, and debug of test failures
• Develop block, IP and SoC level test-benches
• Track and report DV progress using a variety of metrics, including bugs and coverage
• Make use of LLM and related technologies to achieve efficient execution and improved quality

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level