Design Verification Engineer

Broadcom•Fort Collins, CO

About The Position

Broadcom's ASIC Products Division (APD) is seeking an experienced verification engineer to be responsible for modeling and verification activities related to complex digital and mixed signal (MXS) IP blocks used in Broadcom’s ASIC developments. This position involves defining verification plans and environment architecture, developing test cases and test bench components, coverage analysis and closure, and debug. The engineer may also work with emulation and FPGA prototyping platforms and lead efforts in evaluating and driving the adoption of advanced verification methodologies/flows. A key aspect of the role is developing functional models for block, system, and ASIC level verification, working closely with design teams and EDA vendors. The candidate will be expected to design verification components including UVM agents, checkers, and behavioral models, and implement and achieve coverage goals through random & directed test cases and SystemVerilog Assertions. The role also includes analyzing and debugging simulation failures at the RTL and gate-level, requiring knowledge of RTL, gate-level netlists, and SDF for verification context.

Requirements

6+ years of experience with verification concepts and architectures for complex digital and MXS circuits
Experience verifying designs at the block and system levels
Experience with complex digital and mixed-signal circuits (PLL, DLL, ADC, DAC)
Experience debugging RTL and gate-level netlists, analyzing schematic diagrams of analog / MXS circuits
Experience using SystemVerilog and advanced verification concepts and methodologies (UVM, SVA)
Experience with Synopsys, Cadence, and Mentor simulations tools
Demonstrated ability to plan and deploy complex, reusable, and scalable verification environments
Experience with Perl/Python and Tcl or other scripting languages
Experience with version control systems (DesignSync, git)
Superior writing, grammar, and verbal communication skills
Excellent problem solver; develops and employs automated processes where applicable
Worked independently and in a global team and dynamic environment in a highly visible role
Possesses ability to learn and adapt to new tools and methodologies on the fly
Must have legal authorization to work in the US
BS in Electrical Engineering / Computer Engineering and 8+ years of related experience or an MS in Electrical Engineering / Computer Engineering and 6+ years of related experience

Nice To Haves

Experience with hardware design and debug
Experience with emulation (Palladium, Veloce, Zebu) and FPGA (Xilinx) platforms
Formal verification concepts / experience
Experience with verifying iJTAG network using ICL and PDL in the Tessent tool
Experience with co-simulation

Responsibilities

Define verification plans and environment architecture
Develop test cases and test bench components
Perform coverage analysis and closure
Debug issues
Work with emulation and FPGA prototyping platforms
Lead efforts in evaluating and driving the adoption of advanced verification methodologies/flows
Develop functional models to facilitate block, system, and ASIC level verification
Work closely with design teams and EDA vendors to accomplish modeling and verification tasks
Design verification components including UVM agents, checkers, and behavioral models
Implement and achieve coverage goals by developing random & directed test cases, and SystemVerilog Assertions
Analyze and debug simulation failures at the RTL and gate-level