Design Verification Engineer

Broadcom•San Jose, CA

21h

About The Position

The CSG group at Broadcom has brought some of the most complex and cutting edge networking ASIC's and multichip solutions to market over the last decade. The group develops Tomahawk ASICs for Scale-Out and Scale-Up AI Networks. These products support the latest networking protocols and features as well as manage extremely large volumes of traffic of the order of several hundreds of Terabits/sec. These networking ASIC's support a large number of ports ranging from 10/100Mb/s to 1600Gb/s speeds as well as various line interfaces and protocols. The successful candidate will be responsible for various key tasks in the areas of verification of cutting edge network switch routing designs.

Requirements

MSEE or BSEE or equivalent, with concentration in digital design and excellent academic standing. Total engineering minimum experience required is typically a BS degree and 8+ years of experience, an MS degree and 6+ years of experience or a PhD and 3+ years of experience or equivalent.
Familiar with Hardware description languages (Verilog/SystemVerilog/UVM), scripting languages (Perl, Python) and Object Oriented Programming (OOP).
Exposure to cutting edge verification and validation techniques and methodologies using Object Oriented modular reusable environments in languages such as Systemverilog, Perl, Python
Strong understand and prior experience of end-to-end verification process from test plan definition to coverage closure on ASIC/SOC silicon that has gone into mass production
Excellent verbal and written communication skills.

Responsibilities

Participating in the verification processes of L2/L3 Network Switching and routing ASICs and various subsystems within these chips
Understanding the architecture and implementation of these chips and coming up with in depth test plans for verifying various key networking features such as L2/L3 traffic streaming, traffic management, scheduling and shaping of traffic, latency and performance characterization of chips and systems.
Developing verification environments including testbenches and verification API’s associated with the chip architecture to enable testing of various features within the chips as well as scripts and Makefiles as required to run the environment in various tool chains
Implementing test plans into executable test suites using a cutting edge Systemverilog verification environment.
Executing the verification process to completion pre-silicon using various functional and code coverage metrics as measures of completion