Design Engineer - STA

Broadcom•Fort Collins, CO

13d•$129,400 - $207,000

About The Position

Works on significant and unique development and support issues where analysis of situations or data requires an evaluation of intangibles along with an in-depth understanding of the underlying design/constraints and implementation techniques used. Exercises independent judgment in methods, techniques and evaluation criteria for obtaining results. Creates formal networks involving coordination among groups and works well with individuals and teams spread across geographical time-zones. Acts independently to determine methods and procedures on new or special assignments. May supervise the activities of others. Works in close collaboration with supervisor and can effectively context-switch and multi-task based on business need.

Requirements

Strong understanding of VLSI and ASIC physical design
Basic understanding of PLLs and clock networks
Familiarity with design elements like flip flops, latches, memories, and basic CMOS logic gates
Experience using a static timing analysis tool
Ability to create and debug timing constraints
Ability to understand and debug warning and error messages from the timing tool
Ability to generate and understand timing reports
Understanding of basic STA concepts
Solid understanding of RC networks and how they affect the timing/propagation of signals
Understanding of Signal Integrity, Crosstalk Delay, and Glitch/Noise Analysis
Understanding of setup analysis, hold analysis, and other timing checks
Ability to understand and create timing diagrams
TCL coding experience required
Ability to work and clearly communicate with multiple engineers and teams across geographies
Ability to work with and organize large amounts of data
Ability to organize and present data in a clear manner
Ability to manage a large variety of tasks
Strong ability to debug problems and create solutions
BS degree in Electrical Engineering or Computer Engineering and 12+ years related experience; or an MS degree in Electrical Engineering or Computer Engineering and 10+ years related experience.

Nice To Haves

Experience using Synopsys PrimeTime and/or Cadence Tempus
Preferred understanding of more advanced STA concepts
POCV/SOCV/LVF modeling of variation
MIS - multi input switching
CCS/ECSM/NLDM - liberty timing models
PBA - path based analysis
LOCV/SOCV - location aware timing derates
Experience on timing SOIC/ 3DIC designs a plus
Experience using SPICE analysis
Experience with at least one or two other coding languages besides TCL is preferred
Python/Ruby, BASH programming languages

Responsibilities

Strong understanding of VLSI and ASIC physical design
Basic understanding of PLLs and clock networks
Familiarity with design elements like flip flops, latches, memories, and basic CMOS logic gates
Experience using a static timing analysis tool (preferably Synopsys PrimeTime and/or Cadence Tempus)
Ability to create and debug timing constraints
Ability to understand and debug warning and error messages from the timing tool
Ability to generate and understand timing reports
Understanding of basic STA concepts
Solid understanding of RC networks and how they affect the timing/propagation of signals
Understanding of Signal Integrity, Crosstalk Delay, and Glitch/Noise Analysis
Understanding of setup analysis, hold analysis, and other timing checks
Ability to understand and create timing diagrams
Coding experience (TCL required, experience with at least one or two other coding languages preferred)
Ability to work and clearly communicate with multiple engineers and teams across geographies
Ability to work with and organize large amounts of data
Ability to organize and present data in a clear manner
Ability to manage a large variety of tasks
Strong ability to debug problems and create solutions