CPU RTL Power, Clocking, Reset Design Engineer

Advanced Micro Devices, Inc•Fort Collins, CO

About The Position

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. The Role AMD's Core Complex Cache Hierarchy team builds the complexes that connect our compute (execution) cores — each complex combining multiple cores and their L2 caches together with a coherency fabric, optimized for the highest performance and power efficiency in the industry. Within this team, we're looking for an experienced RTL design engineer to serve as our Chip Pervasive Logic expert — owning the power management, clocking, and reset microarchitecture and RTL for these Core Complex designs. The candidate will be a key contributor to AMD's next-generation cores and Core Complexes.

Requirements

Successful experience delivering aggressive goals on aggressive schedules.
Enjoy engaging with many different teams covering a breadth of technical areas.
Creativity, innovation, and excellent verbal and written communication skills.
Strong analytical thinking and problem-solving skills.
Ability and desire to guide and develop people.
Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, or Computer Science, plus experience in RTL design and microarchitecture development for processors or complex IPs.

Nice To Haves

Successful track record delivering high-performance CPU product architecture and implementation, including clocks, power management, reset, clock-domain crossing, and voltage-domain management.
Experience with system management, voltage management and distribution, and clock control architecture, implementation, and tapeout closure.
Experience with SoC development, either directly or through IP delivery, and collaboration across multidisciplinary engineering teams.
Strong background in Digital RTL Design, Verilog HDL, and scripting.

Responsibilities

Collaborate with Architecture, Physical Design, Verification, and Design-for-Test teams to design, document, implement, verify, and deliver high-performance Power, Clocking, Reset, and Control Fabric RTL optimized for timing, testability, manufacturability, and physical implementation.
Work across global IP and SoC teams to solve complex architectural interactions and drive successful product execution.
Improve CPU design quality, performance, power, and area through innovation, simplification of design complexity, and enhanced cross-functional technical collaboration.
Solve complex design and tool challenges using innovative approaches and communicate solutions through technical presentations to peers and management.
Guide, mentor, and develop engineers across the organization.