CPU Physical Design Timing Engineer

Qualcomm • Austin, TX

2d • $186,700 - $280,100

About The Position

NUVIA is now part of Qualcomm. Qualcomm’s mission is to reimagine silicon and create computing platforms that transform the industry. As a CPU Physical Design Timing Engineer, you will define, develop, and drive CPU timing closure for Oryon CPU cores. You will work with microarchitecture and RTL design teams to develop timing constraints and drive implementation toward aggressive power, area, and performance goals using industry-standard tools and flows.

A primary focus is developing scripts for use with static timing analysis (STA) tools to enable CPU timing infrastructure and methodology across multiple CPU projects. You will collaborate with Qualcomm’s central timing technology and methodology team and interact with the CPU implementation team to advance CPU PPA goals. The role offers an opportunity to work on N2/N3 technology nodes.

Requirements

• Excellent automation skills using TCL, Perl, or Python.
• Ability to develop or work on automation scripts from a specification for CPU STA signoff flows and methodology.
• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, and 6+ years of relevant work experience; or a master's degree in one of these fields and 5+ years; or a PhD in one of these fields and 4+ years.
• Good technical writing and communication skills.
• Familiarity with digital implementation flows from RTL to GDS, including ICC, Innovus, and PrimeTime/Tempus.

Nice To Haves

• History of framework, tool, or utility development.
• Strong expertise in STA timing analysis fundamentals, AOCV/POCV concepts, CTS, defining and managing timing constraints, latch transparency, and zero-cycle and multi-cycle path handling.
• Hands-on experience with STA tools such as PrimeTime and Tempus.
• Experience driving timing convergence at chip and hard-macro levels.
• In-depth knowledge of crosstalk noise, signal integrity, layout parasitic extraction, and feed-through handling.
• Knowledge of ASIC back-end design flows, methods, and tools such as ICC2 and Innovus.
• Basic knowledge of device physics.

Responsibilities

• Set up, converge, review, and sign off STA for multi-mode, multi-voltage-domain Oryon CPU core designs.
• Perform timing analysis, validation, and debugging across multiple PVT conditions using PrimeTime and/or Tempus.
• Run PrimeTime and/or Tempus for STA flow optimization and Spice-to-STA correlation.
• Identify root causes of timing miscorrelation at different design levels in functional and test modes, and propose solutions.
• Evaluate timing methodologies and tools across different designs and technology nodes.
• Develop automation scripts according to specifications for CPU STA signoff flows and methodology.
• Collaborate with microarchitecture, RTL design, CPU implementation, and central timing technology and methodology teams.
• Communicate technical information and contribute to a cross-collaborative environment.

Benefits

• Competitive annual discretionary bonus program.
• Opportunity for annual RSU grants; employees on sales-incentive plans are not eligible for the annual bonus.
• Competitive benefits package designed to support employees at work, at home, and at play.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior