CPU Core RTL Design Engineer

Advanced Micro Devices, Inc•Austin, TX

About The Position

As a CPU Core RTL Design Engineer, you will help design and optimize next-generation high-performance processor cores within AMD’s central core RTL team, supporting products across client, server, and AI platforms. Working with architecture, performance, verification, and physical design partners, you will contribute to core pipeline logic and microarchitecture features, with potential focus areas such as load/store or decode based on your expertise. The role affects the performance, power efficiency, and scalability of future CPU designs and involves solving complex technical challenges.

Requirements

  • Experience with Verilog/SystemVerilog RTL development in CPU, SoC, or ASIC environments.
  • Strong understanding of modern CPU architecture, especially out-of-order cores.
  • Expertise in logic design and high-speed processor pipeline development.
  • Knowledge of power-efficient and low-power design techniques, including timing and power optimization.
  • Familiarity with synthesis, place-and-route, and timing closure.
  • Experience debugging and optimizing designs in collaboration with performance and verification teams.
  • Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field is preferred.

Nice To Haves

  • Experience with load/store, cache hierarchy, address translation/TLB, prefetch, branch prediction, or similar core subsystems.
  • Exposure to the full product lifecycle, from architecture through post-silicon debug.
  • Familiarity with physical design, scripting (e.g., Python, Tcl), and concepts such as DFT, clocking, reset, and power management.

Responsibilities

  • Design and implement RTL for CPU core pipeline components and related logic.
  • Contribute to microarchitecture definition for next-generation processor cores.
  • Collaborate with architecture, verification, and performance teams to deliver optimized designs.
  • Analyze and improve performance, power, and timing characteristics.
  • Support design verification, synthesis, timing closure, and physical design efforts.
  • Debug and resolve pre-silicon and post-silicon issues.
  • Partner with cross-functional teams to align on design trade-offs and execution.
  • Contribute to scalable RTL methodologies, libraries, and best practices.

Benefits

  • AMD benefits are described in “AMD benefits at a glance.”
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