CPU RTL Design Engineer

Intel Corporation•Austin, TX

1d•$105,650 - $200,340•Hybrid

About The Position

Join Intel's CPU design team to develop processors for the next generation of computing. The CPU RTL Design Engineer contributes to logic design, microarchitecture, and RTL development for Intel processors. The role involves developing and optimizing RTL, validating design functionality through simulation and debugging, and collaborating with architecture, verification, physical design, and SoC integration teams to deliver high-quality CPU designs. The work also offers opportunities to build expertise in CPU architecture, microarchitecture, digital logic design, SystemVerilog/Verilog, and power, performance, area, and timing optimization.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field and 3+ years of relevant experience; OR a master's degree in the same field and 1+ years of relevant experience; OR a PhD in the same field with 3+ months of educational experience.
Experience with digital logic design and RTL development.
Experience coding in SystemVerilog and/or Verilog.
Experience with RTL simulation, functional validation, and/or debugging.
Experience with architecture, microarchitecture, or digital design concepts.

Nice To Haves

Experience developing or working from microarchitecture specifications.
Experience working with design verification and debugging RTL failures.

Responsibilities

Develop and implement high-quality logic designs for CPU features that comply with architecture and microarchitecture specifications.
Write and optimize RTL to meet power, performance, area, and timing goals for physical design implementation.
Collaborate with architecture teams to define and refine CPU microarchitectural features.
Review verification plans, analyze test results, and resolve failing RTL tests to ensure feature correctness.
Document microarchitectural specifications (MAS) for CPU designs.
Support SoC customers to ensure seamless integration of CPU designs into larger systems.