ASIC/RTL Design Engineer V

TekWissen • San Jose, CA

18h • Onsite

About The Position

The ASIC/RTL Design Engineer V drives low-power design strategies, synthesis, and timing closure for complex SoC and IP designs. The role uses industry-standard electronic design automation (EDA) tools to optimize power, performance, and area (PPA), helping ensure efficient, reliable silicon that meets product requirements. The position is based onsite in San Jose, California, and is a 12-month temporary assignment.

The engineer develops power-reduction strategies, performs synthesis and static timing analysis, analyzes dynamic and leakage power, and collaborates with RTL design, physical design, and verification teams. The role also includes low-power verification and sign-off support, workflow automation, and test-plan documentation that accounts for interactions with other features and hardware. The successful candidate is detail-oriented, analytical, collaborative, and interested in digital design and power optimization.

Requirements

• Strong background in ASIC synthesis and static timing analysis (STA).
• Hands-on expertise with EDA tools such as Synopsys Design Compiler, PrimeTime, PrimePower, Power Artists, or equivalent.
• Experience with power analysis and optimization techniques, including clock gating, multi-Vt, power gating, and multi-voltage design.
• Familiarity with UPF/CPF power-intent specification and verification.
• Solid understanding of digital design fundamentals and RTL coding in Verilog/SystemVerilog.
• Proficiency in scripting languages such as TCL, Perl, Python, or Shell for flow automation.
• Experience with Verilog, SystemVerilog, C, and C++.
• Ability to automate workflows in a distributed compute environment.

Nice To Haves

• Experience with advanced process nodes such as 7nm, 5nm, or 3nm.
• Exposure to floorplanning, place-and-route, and ECO flows.
• Knowledge of low-power design methodologies and trade-offs.
• Prior leadership, mentorship, or cross-functional collaboration experience.
• Graphics pipeline knowledge.

Responsibilities

• Develop and implement power-reduction strategies across SoC/IP designs.
• Perform synthesis and static timing analysis (STA) to achieve PPA targets.
• Analyze and optimize dynamic and leakage power using industry-standard tools.
• Work with RTL designers, physical design, and verification teams to meet timing and power requirements.
• Run low-power verification checks using UPF/CPF and validate power-intent implementation.
• Support sign-off activities for lint, CDC, synthesis, timing, and power closure.
• Automate and streamline power and timing workflows.
• Build test-plan documentation that accounts for interactions with other features and hardware.

What This Job Offers

• Career Level: Senior
• Education Level: No Education Listed