ASIC Research Engineer- Front-End Digital Design

University of Southern California • Arlington, VA

4d • $115,000 - $140,000 • Onsite

About The Position

USC’s Information Sciences Institute (ISI), a unit of the Viterbi School of Engineering, is hiring an ASIC Research Engineer for its CS&T Division in Arlington, Virginia. The role performs front-end digital design of advanced ASIC prototypes addressing problems of national importance. The engineer will work with a cutting-edge team to design and verify register-transfer-level (RTL) models of CPUs, memories, and accelerators for communications, signal processing, and security applications. The work is based in ISI’s Arlington office.

The engineer may collaborate with ISI’s MOSIS 2.0 service, integrate third-party IP cores, and work with research sponsors including DARPA, IARPA, and the CHIPS Act. The position offers a collaborative, flexible university setting, opportunities to learn and grow, and exposure to a fast-moving research environment. The minimum education is a bachelor’s degree, with combined experience and education accepted as a substitute; minimum experience is three years. A master’s degree and five years of experience are preferred. The annual base salary range is $115,000 to $140,000.

Requirements

• Ability to handle Controlled Unclassified Information (CUI); eligibility requires U.S. citizenship or permanent residency under U.S. government regulations.
• Bachelor’s degree in Computer Engineering, Electrical Engineering, or a related field with more than 3 years of experience, or a master’s degree.
• Demonstrated excellence creating digital designs with Verilog, SystemVerilog, or VHDL RTL.
• Solid understanding of computer architecture and microarchitecture.
• Demonstrated skills with EDA tools, scripting, and revision control.
• Experience with Linux.

Nice To Haves

• Experience using logic synthesis and timing tools.
• Familiarity with digital design verification.
• Familiarity with performance modeling.
• Familiarity with agile hardware design methodologies.
• Experience with AI-assisted workflows.
• Experience using FPGAs.
• Effective verbal communication and ability to give clear explanations.
• Master’s degree.
• Five years of experience.
• Proven leadership ability.
• Experience with artificial intelligence, very large-scale integration design, machine learning, deep learning (e.g., TensorFlow, PyTorch, HuggingFace), and Dockerization.

Responsibilities

• Design and verify RTL models of CPUs, memories, and accelerators.
• Perform front-end digital design of advanced ASIC prototypes.
• Integrate third-party IP cores.
• Collaborate with ISI’s MOSIS 2.0 service and research sponsors.

Benefits

• Opportunities for free, top-tier university education for the employee and their children.
• Medical benefits.
• Matched retirement benefits.
• Quality work-life balance.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level