Senior ASIC Research Engineer – Front-end Digital Design

University of Southern California • Arlington, VA

4d • Onsite

About The Position

USC’s Information Sciences Institute (ISI), part of the Viterbi School of Engineering, is hiring a Senior ASIC Research Engineer for its Computational Systems & Technology Division in Arlington, Virginia. The engineer will design advanced ASIC prototypes addressing problems of national importance and work with a team to design and verify RTL models of CPUs, memories, and accelerators for applications such as communications, signal processing, and security.

The position offers opportunities to collaborate with ISI’s MOSIS 2.0 service, integrate third-party IP cores, and work with research sponsors including DARPA, IARPA, and the CHIPS Act. The role is based in ISI’s Arlington office and offers a collaborative university research setting with learning and growth opportunities.

Requirements

• Ability to handle Controlled Unclassified Information (CUI); eligibility requires U.S. citizenship or permanent residency.
• Degree in Computer Engineering, Electrical Engineering, or a related field.
• Master’s degree with more than 5 years of experience (listed under minimum qualifications).
• Demonstrated excellence creating digital designs with Verilog, SystemVerilog, or VHDL RTL.
• Solid understanding of computer architecture and microarchitecture.
• Demonstrated skills with EDA tools for logic synthesis and timing, scripting, and revision control.
• Bachelor’s degree, with combined experience and education accepted as a substitute for minimum education (listed under minimum education).
• Minimum 8 years of experience (listed under minimum experience).
• Experience with Linux.
• Excellent written and oral communication skills.

Nice To Haves

• Familiarity with digital design verification.
• Familiarity with performance modeling.
• Familiarity with agile hardware design methodologies.
• Experience with AI-assisted workflows.
• Experience using FPGAs.
• Effective verbal communication and ability to give clear explanations.
• Master’s degree (listed under preferred education).
• 10 years of experience (listed under preferred experience).
• Proven leadership ability.
• Experience with artificial intelligence, very large-scale integration design, machine learning, deep learning (e.g., TensorFlow, PyTorch, HuggingFace), and Dockerization.

Responsibilities

• Design advanced ASIC prototypes.
• Design and verify RTL models of CPUs, memories, and accelerators.
• Integrate third-party IP cores.
• Collaborate with ISI’s MOSIS 2.0 service.

Benefits

• Opportunities for free, top-tier university education for the employee and their children.
• Great benefits, including medical coverage and matched retirement.
• Quality work-life balance.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior