Senior ASIC Research Engineer – Front-end Digital Design

University of Southern California • Arlington, VA

5d • $140,000 - $170,000 • Onsite

About The Position

USC’s Information Sciences Institute (ISI), within the Viterbi School of Engineering, is hiring a Senior ASIC Research Engineer for its Computational Systems & Technology Division. The role designs advanced ASIC prototypes addressing problems of national importance. The engineer will work with a team to design and verify RTL models of CPUs, memories, and accelerators for communications, signal processing, and security applications. The position offers opportunities to collaborate with ISI’s MOSIS 2.0 service, integrate third-party IP cores, and work with research sponsors including DARPA, IARPA, and the CHIPS Act. It is based in ISI’s Arlington, Virginia office and offers a collaborative university research setting with learning and growth opportunities.

Requirements

• Ability to handle Controlled Unclassified Information (CUI); eligibility requires U.S. citizenship or permanent residency.
• Degree in Computer Engineering, Electrical Engineering, or a related field.
• Master’s degree with more than 5 years of experience (minimum qualifications).
• Demonstrated excellence creating digital designs using Verilog, SystemVerilog, or VHDL RTL.
• Solid understanding of computer architecture and microarchitecture.
• Demonstrated skills with EDA tools for logic synthesis and timing, scripting, and revision control.
• Minimum education listed as a bachelor’s degree, with combined experience/education accepted as a substitute.
• Minimum experience listed as 8 years.
• Experience with Linux.
• Excellent written and oral communication skills.

Nice To Haves

• Familiarity with digital design verification.
• Familiarity with performance modeling.
• Familiarity with agile hardware design methodologies.
• Experience with AI-assisted workflows.
• Experience using FPGAs.
• Effectiveness in verbal communication and giving clear explanations.
• Preferred education: Master’s degree.
• Preferred experience: 10 years.
• Proven leadership ability.
• Experience with artificial intelligence, very large-scale integration design, machine learning, deep learning (e.g., TensorFlow, PyTorch, HuggingFace), and Dockerization.

Responsibilities

• Design advanced ASIC prototypes.
• Design and verify RTL models of CPUs, memories, and accelerators.
• Integrate third-party IP cores.
• Collaborate with ISI’s MOSIS 2.0 service and research sponsors.

Benefits

• Opportunities for free, top-tier university education for the employee and their children.
• Medical benefits.
• Matched retirement benefits.
• Quality work-life balance.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior