Digital ASIC Design Engineer

The Charles Stark Draper Laboratory•Cambridge, MA

1d•Onsite

About The Position

Draper is an independent, nonprofit research and development company headquartered in Cambridge, Massachusetts, with more than 2,000 employees. Its multidisciplinary teams develop solutions to national challenges across fields including defense, space exploration, and biomedical engineering. The Digital ASIC Design Engineer specifies, designs, verifies, tests, and documents application-specific integrated circuits. The role includes developing architectures, designing circuits and/or HDL, performing simulations, and verifying and testing designs. The engineer contributes to system-level design, optimizes hardware for performance, power, and cost, and evaluates the feasibility of implementing complex algorithms and requirements. The position also involves independently advancing complex chip architectures and solutions, contributing to business development and proposals, and documenting and teaching best practices to less experienced engineers. The position requires a current, active US Secret Clearance. Selected applicants must obtain and maintain a government security clearance. The role is based in Cambridge, Massachusetts. The US base salary range for this full-time position is $62,500 to $156,000. Individual pay depends on location and factors such as job-related skills, experience, education, and training. Draper supports work-life balance through workplace flexibility, employee clubs, health and finance workshops, off-site social events, and discounts to local museums and cultural activities. Draper is committed to an inclusive environment and equal opportunity, and provides reasonable accommodations for individuals with disabilities.

Requirements

Current, active US Secret Clearance is required; selected applicants must obtain and maintain a government security clearance.
Bachelor's degree in Engineering or a related field, or a master's degree or PhD as applicable to the experience pathways listed.
Requires 5–7 years of ASIC Hardware Engineering or related experience with a bachelor's degree, 3–5 years with a master's degree, or 0–2 years with a PhD.
Solid skills in front-end digital systems design.
Experience with design flows from Cadence or Synopsys.
Fluency in SystemVerilog, Verilog, or VHDL.
Familiarity with LINT, simulation, and synthesis.
Proficiency in integrated circuit design and understanding of integrated circuits, semiconductors, and general computer architecture.
Ability to write detailed design specifications and manage small technical teams.
Excellent verbal and written communication, mathematical, organizational, and time-management skills, including the ability to meet deadlines.
Strong analytical and problem-solving skills and ability to prioritize tasks.
Strong organization, planning, and time-management skills to achieve program goals.

Nice To Haves

Master's degree preferred.
Familiarity with architectures for secure systems design, such as cryptographic encoders/decoders or tagged processor architectures.
Demonstrated experience with successful tape-outs at advanced nodes.
Experience leading and managing design teams.

Responsibilities

Contribute to system-level design.
Optimize hardware designs for performance, power, and cost.
Evaluate the hardware feasibility of complex algorithms and requirements.
Independently contribute to complex chip architectures and designs.
Independently drive solutions to complex problems, develop requirements, propose ways forward when customer requirements are unclear or incomplete, and adapt to changes in requirements.
Contribute to business development and proposal activities.
Develop, document, and teach best practices to less experienced engineers.
Perform other duties as assigned.
Specify, design, verify, test, and document application-specific integrated circuits.
Develop architectures, design circuits and/or HDL, perform simulations, and verify and test designs.