ASIC Research Engineer- Front-End Digital Design
About The Position
USC’s Information Sciences Institute (ISI), a unit of the Viterbi School of Engineering, is seeking an ASIC Research Engineer for front-end digital design in its CS&T Division. The engineer will design and verify register-transfer level (RTL) models of CPUs, memories, and accelerators for applications including communications, signal processing, and security, contributing to advanced ASIC prototypes that address problems of national importance. The role involves collaboration with a cutting-edge team and may include work with ISI’s MOSIS 2.0 service and integration of third-party IP cores. The engineer will have opportunities to gain experience with research sponsors such as DARPA, IARPA, and the CHIPS Act in a collaborative university research setting with learning and growth opportunities. The work will be based in ISI’s Arlington, Virginia office.
Requirements
- Ability to handle Controlled Unclassified Information (CUI); eligibility requires U.S. citizenship or permanent residency.
- Degree in Computer Engineering, Electrical Engineering, or a related field.
- Bachelor’s degree with more than 3 years of experience, or a Master’s degree.
- Demonstrated excellence creating digital designs with Verilog, SystemVerilog, or VHDL RTL.
- Solid understanding of computer architecture and microarchitecture.
- Demonstrated skills with EDA tools, scripting, and revision control.
- Experience with Linux.
Nice To Haves
- Experience using logic synthesis and timing tools.
- Familiarity with digital design verification.
- Familiarity with performance modeling.
- Familiarity with agile hardware design methodologies.
- Experience with AI-assisted workflows.
- Experience using FPGAs.
- Effective verbal communication and ability to give clear explanations.
- Preferred education: Master’s degree.
- Preferred experience: 5 years.
- Proven leadership ability.
- Experience with artificial intelligence, very large-scale integration design, machine learning, deep learning (e.g., TensorFlow, PyTorch, HuggingFace), and Dockerization.
Responsibilities
- Design digital components for advanced ASIC prototypes.
- Create and verify RTL models of CPUs, memories, and accelerators.
- Contribute to projects involving communications, signal processing, and security.
- Collaborate with ISI’s MOSIS 2.0 service and integrate third-party IP cores as applicable.
Benefits
- Opportunities for free, top-tier university education for the employee and their children.
- Great benefits, including medical coverage and matched retirement.
- Quality work-life balance.
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
