ASIC Physical Design, Principal Engineer

Synopsys•Sunnyvale, CA

25d•$197,800 - $296,700•Onsite

About The Position

Synopsys is hiring a Principal Engineer to own physical integration for advanced SerDes IP, from floorplanning through GDSII. The role focuses on timing closure, power optimization, and signoff at 16nm and below, supporting 56G, 112G, and 224G PAM4/6 SerDes across FinFET nodes. The engineer will work closely with front-end, analog, CAD, verification, product, and customer teams to resolve integration challenges and support successful tapeouts. The position includes developing and validating timing constraints, clock architectures, and low-power techniques to meet customer power, performance, and area targets. It also involves leading customer engagements on SoC integration planning, constraint delivery, and tapeout support; improving methodologies and automation; debugging analog-digital interface issues; and mentoring engineers. The role contributes to future SerDes product direction through lessons learned from tapeouts and customer integration challenges. The role is part of the Enterprise SerDes IP team, which delivers high-speed interface IP and collaborates across internal functions and with customers. International travel may be needed for customer engagements or team collaboration. The position is based in Sunnyvale, California and is not remote eligible.

Requirements

MSEE with 10+ years or BSEE with 12+ years of digital or physical design experience, including recent contributions to project tapeouts.
Deep hands-on experience with the full RTL-to-GDSII flow, including chip-level integration, timing closure, and physical signoff.
Experience with advanced FinFET nodes (TSMC 16nm or below), including low-power design techniques and process-specific challenges.
Strong understanding of timing constraint development, clock architecture, and design techniques for meeting power and area targets.
Experience leading technical initiatives or projects and delivering results on schedule.
Understanding of digital and mixed-signal verification flows, SoC integration challenges, and analog-digital interface considerations.
Strong scripting and automation skills in Perl, Tcl, or Python, with a methodology-driven approach to design and CAD flows.
Ability to communicate complex physical-design tradeoffs to analog engineers, front-end architects, and customer program managers.
Comfort with making and owning decisions when information is incomplete.

Responsibilities

Own physical integration of advanced SerDes IP from floorplanning through GDSII, including timing closure, power optimization, and signoff at 16nm and below.
Drive RTL-to-GDSII flows for 56G, 112G, and 224G PAM4/6 SerDes across FinFET nodes in collaboration with front-end, analog, and CAD teams.
Develop and validate timing constraints, clock architectures, and low-power design techniques to meet customer PPA targets and support first-pass silicon success.
Lead customer engagements on physical integration, including SoC-level integration planning, constraint delivery, and tapeout support.
Build and improve design methodologies, automation scripts, and flows to reduce customer effort and improve delivery predictability.
Debug and resolve analog-digital interface issues with analog design and verification teams.
Mentor engineers on physical design best practices, timing closure strategies, and advanced-node challenges.
Identify architectural and flow improvements based on tapeout learnings and customer integration challenges.
Collaborate with front-end design, analog engineering, CAD, product teams, and internal and external customers.
Travel internationally when required for customer engagements or team collaboration.