ASIC/FPGA Design and Verification Engineer - (Lead, Senior, or Principal)

Boeing•Albuquerque, NM

2d•$136,850 - $266,800•Onsite

About The Position

Boeing Space, Intelligence & Weapons Systems is seeking ASIC/FPGA Design or Verification Engineers (Lead, Senior, or Principal) to join the Boeing Electronic Products team in Albuquerque, NM. This team develops ASICs and FPGAs that are integral to Boeing's products, ranging from satellite systems to commercial airplane equipment. The group utilizes leading-edge technology to create complex SoCs and custom processors, including ARM IP for flight computers, applying advanced digital IC design processes. The diverse portfolio offers exposure to various Boeing business units such as Space & Launch, AvionX, Missiles & Weapons, Strike, Surveillance and Mobility, and Autonomous Systems. As an ASIC/FPGA Engineer, you will develop state-of-the-art digital ICs/SoCs for critical programs. The team is expanding and hiring at all levels due to a high volume of new projects. Collaboration occurs with electronics groups globally, supporting both in-house and externally designed electronics. Within the LEOS team, work involves high-performance laser gimbal control systems, encompassing FPGA design and embedded software development, with a focus on seamless hardware-software integration.

Requirements

Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement.
9+ years of ASIC/FPGA design or verification experience (or minimum Master’s and 7+ years of ASIC/FPGA design or verification experience).
Experience with ASIC/FPGA architectural definition, and detailed design implementation and functional verification using SystemVerilog with delivery/release of production designs.
Professional experience with hardware-based integration and test of ASIC/FPGA designs.
Ability to obtain a US Security Clearance for which the US Government requires US Citizenship as a condition of employment. An interim and/or final U.S. Secret Clearance Post-Start is required.
Must satisfy the Company’s Conflict of Interest (COI) assessment process.
Must meet U.S. export control compliance requirements. To meet U.S. export control compliance requirements, a “U.S. Person” as defined by 22 C.F.R. §120.62 is required. “U.S. Person” includes U.S. Citizen, U.S. National, lawful permanent resident, refugee, or asylee.

Nice To Haves

Senior, Level 5: 14+ years of related work experience or an equivalent combination of education and experience.
Principal, Level 6: 20+ years of related work experience or an equivalent combination of education and experience.
Master's Degree in EE, Computer Engineering/Science, or related field, or equivalent experience.
Proven record of leading ASIC/FPGA design and/or verification teams, including tracking and reporting progress to stakeholders.
Experience with hardware emulators, especially Palladium.
Proficiency with hardware verification languages: System Verilog, System Verilog Assertions.
Ability to executable test plans.
Proficiency with Object Oriented Programming Concepts: Inheritance, Polymorphism, etc.
Ability to create self-checking and reusable testbenches from scratch.
Experience developing Functional Coverage Models and Closing Code Coverage.
Experience with high-speed Serdes interfaces (JESD204C, PCIe, Ethernet).
Proficient in scripting languages: Make, Perl, Python, etc.
Revision Control Systems: svn, cvs, git.
Proficient in Linux Environments.
Familiarity with space-based design techniques and radiation mitigation.
Demonstrated history of 1st pass success with ASIC designs.

Responsibilities

Conduct unit-level testing, verification, and validation of embedded software and firmware, utilizing debugging tools like oscilloscopes and logic analyzers to identify and resolve issues.
Create and maintain technical documentation, including requirements documents, design specifications, test plans, and interface control documents.
Support the integration of software and hardware components, from initial hardware bring-up to final system validation.
Analyze and enhance the efficiency, stability, scalability, and performance of system resources, often within the constraints of low power or memory.
Lead FPGA/ASIC designs, including multi-FPGA/ASIC programs and teams with design and verification engineers, and manage team execution to meet program milestones.
Collaborate with customers, system engineers, and hardware engineers to drive requirements capture and architect digital logic functions to meet mission/customer needs.
Explore trade-space of potential ASIC/FPGA technologies and determine the optimal parts, weighing Schedule, Cost, Risk, Area, Power (SCRAP) vs. performance.
Implement FPGA/ASIC with latest design practices and tools from block-level micro-architecture, through HDL coding, and physical design realization (through gate-level netlists for ASIC designs).
Integrate DSP IP from Boeing’s algorithm team and third-party IP as needed.
Perform static timing analysis, LEC, CDC, linting, and other necessary checks to ensure the design is completed on schedule.
Develop Functional Coverage Models and perform Code Coverage to verify designs in simulation.
Create self-checking and reusable test benches from scratch, applying Object Oriented Programming concepts such as Inheritance and Polymorphism, and leverage UVM to create drivers, monitors, predictors, and scoreboards.
Drive FPGA-based prototyping and validation depending on program and system requirements and complexity.
Validate design through hardware integration test with special test equipment, test-beds, and higher-level systems as needed.
Train and mentor less senior engineers across the department and help build effective project teams.