ASIC / FPGA Design Verification Engineer - (Associate or Experienced)

Boeing•El Segundo, CA

2d•$98,600 - $162,150•Onsite

About The Position

Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for multiple ASIC and/or FPGA Design Verification Engineers to join our Boeing Electronic Products team in El Segundo or Huntington Beach, CA. The mission is to develop adaptable verification engineers who build strong technical fundamentals, become independent owners of assigned scope, and grow from guided execution toward ownership of verification work of moderate complexity. Engineers will support ASIC, FPGA, and SoC verification activities across advanced aerospace programs including space systems, satellite technologies, NASA mission support, aviation platforms, communications systems, and related digital subsystems, while gaining exposure to broader digital product development activities. Candidates are expected to possess strong verification fundamentals including simulation concepts, debug methods, coverage approaches, requirements traceability awareness, and general digital verification methodology concepts. Experience with UVM is strongly preferred, and engineers should be prepared to discuss verification fundamentals, SystemVerilog usage, coverage strategy, reusable verification concepts, and their current level of UVM understanding during interviews. Engineers are expected to communicate status, blockers, assumptions, risks, and learning needs proactively while developing increasing ownership. The role emphasizes growth toward independent execution and effective management of personal scope of work. Teams combine engineers with complementary technical strengths. Engineers are encouraged to build deeper expertise in selected areas while collaborating across broader verification activities to support overall program goals.

Requirements

Ability to obtain a US Security Clearance for which the US Government requires US Citizenship as a condition of employment. An interim and/or final U.S. Secret Clearance Post-Start is required.
Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement
Bachelor’s degree with 2+ years of professional engineering experience in ASIC, FPGA, or SoC design verification, OR a Master’s degree with related verification project/coursework experience
Understanding of digital verification fundamentals
Experience with SystemVerilog for simulation testbench development and RTL debugging

Nice To Haves

Experienced, Level 3: 5+ years of related engineering experience
Bachelor’s degree in EE, CE, or related field & 2+ years ASIC, FPGA, or SoC verification experience
Active U.S. Secret Security Clearance
UVM experience strongly preferred
OOP experience strongly preferred
Coverage-driven verification exposure
Requirements traceability experience
Reusable UVC development exposure
System-level debug exposure
Strong communication and technical presentation skills

Responsibilities

Execute assigned verification tasks and progressively increase ownership.
Develop simulation, debug, coverage, and requirements traceability skills.
Contribute to SystemVerilog and UVM environments, tests, UVCs, and reusable infrastructure.
Support integration investigations and system-level debug activities.
Contribute to verification objectives, coverage assessments, and closure activities appropriate to experience level.
Own verification scope of moderate complexity at Level III.
Support assigned verification activities while developing increasing ownership, stronger technical depth, and broader understanding of the verification lifecycle.
Contribute to simulation, debug, coverage assessment, requirements traceability activities, integration support, and closure efforts appropriate to experience level.
Build proficiency in SystemVerilog, UVM environments, reusable verification infrastructure, UVC development, and broader verification methodologies over time.
Independently own verification scope of moderate complexity, communicate risks and dependencies proactively, support integration investigations and system-level debug activities, and contribute to verification objectives and closure activities while continuing to broaden technical capability.