Principal Engineer - FPGA/ASIC Design

Rolls-Royce•Washington, DC

1d•$152,033 - $247,054•Hybrid

About The Position

Rolls-Royce is seeking a Principal Engineer - FPGA/ASIC Design (Field Programmable Gate Arrays / Application Specific Integrated Circuit) Design Specialist to join their team. This role involves working on flagship Rolls-Royce programs and addressing complex technological challenges within a global, multi-disciplinary team. The position is eligible for a hybrid work schedule, requiring a secure internet connection and appropriate workspace. The engineer will design, verify, integrate, and test FPGA/ASIC solutions for current and future engine control system products, including developing architectures, coding, simulations, synthesis, test benches, and documentation for certification authorities.

Requirements

Bachelor's degree in Electronics Engineering and/or Computer Engineering with 5+ years of experience, OR Master's degree in Electronics Engineering and/or Computer Engineering with 3+ years of experience, OR PhD in Electronics Engineering and/or Computer Engineering
Must be a U.S. Citizen

Nice To Haves

Validate the FPGA hardware in the lab using test equipment (oscilloscopes, logic analyzers) and debug tools (e.g ILA, JTAG)
Experience in scripting with languages such as TCL, Python, Shell scripts
Able to work with Windows and Linux development environment
Demonstrable experience in version control, such as Git, SVN
Experience of Actel & Xilinx tool flows to implement complete designs
Development of model-based systems with digital engineering toolsets (MATLAB, Simulink and/or similar)
Knowledge of systems engineering, and robust design tools and techniques coupled with the latest model-centric development approaches
Experience with Cameo Systems Modeler (MagicDraw) or similar SysML modelling software

Responsibilities

Participate in all phases of project, to produce detailed design documentation, verification plans and reports
The design and development of all custom digital devices (ASIC or FPGA), to support RR electronic engine control units
The verification of complex products that use FPGAs and/or ASICs to DO-254
Develop RTL utilizing a hardware description language (e.g. VHDL, Verilog, and/or SystemVerilog) and debug the design via simulation tools
Expertise achieving timing closure on FPGA designs and generating test benches
Evaluate the process flow including but not limited to high level design, synthesis, place and route, timing constraints and power utilization