ASIC / FPGA Digital Design Engineer – (Lead or Senior)
About The Position
Boeing Space, Intelligence & Weapons Systems is seeking multiple ASIC/ FPGA Digital Design Engineers (Lead or Senior) to join their Electronic Products team. This role involves advanced digital subsystem development in an aerospace environment, supporting programs in space, aviation, communications, and autonomous systems. Engineers will work on ASICs, SoCs, and FPGAs across various concurrent programs, collaborating with teams on next-generation satellite systems, NASA missions, Space Launch System technologies, commercial and military aircraft, and autonomous aviation technologies. The department's expertise covers requirements development, architecture, RTL design, ASIC development, FPGA implementation, timing analysis, verification collaboration, integration support, and system-level troubleshooting. There are opportunities to grow from focused contributors to broader technical ownership, subsystem responsibilities, mentorship, and technical leadership roles.
Requirements
- Ability to obtain a US Security Clearance (requires US Citizenship)
- Bachelor of Science degree in Engineering (Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or equivalent
- Bachelor’s degree and 9+ years of experience with FPGA, ASIC, or SoC digital design; or a BS/MS and 7+ years of FPGA, ASIC, or SoC digital design experience
- Experience with HDL development, simulation, debug, and synthesis
- Strong digital design fundamentals (projects with digital logic design, computer architecture, etc.)
- Experience troubleshooting digital systems (debugging RTL design, HDL/architecture)
- Understanding of timing fundamentals and CDC concepts
Nice To Haves
- Senior, Level 5: 14+ years of related engineering experience
- Bachelor's Degree or Master's Degree in EE, Computer Engineering/Science, or related field
- Requirements development and traceability experience
- FPGA implementation including constraints and timing closure
- Static timing analysis experience
- Verification collaboration experience
- High-speed interfaces, processor integration, memory subsystems, or SoC integration
- Mentoring or technical leadership exposure
- Familiarity with industry-standard tools and methodologies
Responsibilities
- Support ASIC, FPGA, or mixed ASIC/FPGA developments depending on assignment
- Contribute to requirements development, refinement, interface definition, conceptual architecture activities, and traceability efforts appropriate to role level
- Develop HDL / RTL for ASIC, FPGA, and SoC systems
- Compile, simulate, debug, and troubleshoot digital designs
- Perform and/or support synthesis, implementation, constraints development, timing closure, and tool execution activities
- Collaborate with verification teams to support simulation, debug, coverage, and integration goals
- Apply timing concepts, CDC fundamentals, and integration considerations
- Support broader system troubleshooting and integration activities
- Communicate technical status, risks, dependencies, and tradeoffs proactively
- Support subsystem ownership activities
- Mentor others
- Lead larger technical efforts, integration activities, or technical teams
- Provide technical leadership
- Support architecture direction and broader technical ownership
- Lead teams, subsystem efforts, and cross-functional initiatives
Benefits
- health insurance
- flexible spending accounts
- health savings accounts
- retirement savings plans
- life and disability insurance programs
- paid and unpaid time away from work
Stand Out From the Crowd
Upload your resume and get instant feedback on how well it matches this job.
What This Job Offers
Job Type
Full-time
Career Level
Senior
