ASIC Engineering Intern, Formal Verification
About The Position
Meta is seeking an ASIC Engineering Intern, Formal Verification, for its Infrastructure Silicon organization. The organization builds infrastructure that supports Meta’s servers, data centers, and services. In this internship, you will work with an ASIC team building accelerators for major workloads, applying formal verification tools and methods to IPs and subsystems. With guidance from experienced ASIC engineers, you will contribute to formal verification planning, assertion and testbench development, and proof analysis for a scoped project. You will learn to translate design intent into properties, analyze counterexamples, and help establish hardware correctness. The internship lasts 12 to 16 weeks.
Requirements
- Currently has, or is in the process of obtaining, a bachelor’s degree in Electrical Engineering, Computer Engineering, or a related engineering field.
- Knowledge of computer architecture and digital logic design fundamentals, including sequential logic and finite-state machines.
- Knowledge of a hardware description language such as Verilog, SystemVerilog, or VHDL.
- Familiarity with assertion-based verification or formal verification concepts, such as properties, assumptions, and counterexamples.
- Critical and creative thinking about how to verify designs and solve problems.
- Must obtain work authorization in the country of employment by the time of hire and maintain ongoing work authorization during employment.
- Intent to return to a degree program after completing the internship.
Nice To Haves
- Currently has, or is in the process of obtaining, a master’s or PhD degree in Electrical Engineering, Computer Engineering, or a related engineering field.
- Coursework, academic projects, or research involving formal methods, hardware verification, or assertion-based verification.
- Experience writing SystemVerilog Assertions or using formal property-checking tools such as Cadence JasperGold, Synopsys VC Formal, or Siemens Questa Formal.
- Experience with open-source formal verification tools and engines such as SymbiYosys, ABC, or Boolector.
- Familiarity with bounded model checking, induction, safety and liveness properties, or techniques such as abstraction and assume-guarantee reasoning.
- Scripting experience with Python, Tcl, Perl, or Shell to automate verification tasks.
- Experience using AI coding agents such as Claude Code or Codex to develop, debug, or automate engineering workflows.
- Exposure to data center application designs such as AI/ML accelerators, networking, or video processing ASICs.
- Familiarity with revision control systems such as Mercurial (Hg), Git, or SVN.
Responsibilities
- Develop an understanding of the architecture, microarchitecture, and intended behavior of designs under verification.
- Contribute to formal verification plans by identifying design requirements, properties to prove, and scenarios to cover.
- Write SystemVerilog Assertions (SVA), assumptions, and cover properties to verify functionality, protocol behavior, and corner cases.
- Develop formal testbenches and harnesses, including clock, reset, and environment models, with guidance from experienced engineers.
- Run formal verification tools, analyze proof results, and debug counterexamples to distinguish design bugs from property or environment issues.
- Help improve proof convergence and assess formal coverage, including checking for vacuous assertions, unreachable scenarios, and overly restrictive assumptions.
- Develop scripts to automate formal runs, regressions, and results analysis.
- Collaborate with design and verification engineers to resolve issues and confirm fixes.
Benefits
- Benefits are offered; specific benefits are not listed.
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What This Job Offers
Job Type
Full-time
Career Level
Intern
