ASIC Digital Design Tech Lead

Cisco•Carlsbad, CA

3d•$166,300 - $238,300

About The Position

The Digital Design Technical Leader for Silicon One Optics will architect digital designs for next-generation optical interconnects and own the ASIC lifecycle from concept through tapeout and post-silicon production. The role leads cross-functional engineering teams spanning digital, analog, firmware, and physical design. The position defines digital architectures, integrates high-speed IP such as ODSP, D2D IP, and SerDes XSR/PAM4, and optimizes power and performance for 100G, 200G, and 400G silicon photonics and Co-Packaged Optics. The technical leader also drives technical strategy and interconnect innovation.

Requirements

Bachelor's degree and 8 years of related experience, or Master's degree and 6 years of related experience, or PhD and 3 years of related experience.
Prior digital design experience with FSMs, CPU subsystems, complex SoCs, and FPGA validation.
Prior experience managing the complete ASIC/SoC design flow.
Prior experience with bus and interface protocols such as SPI, I2C, APB, and AXI, as well as high-speed SerDes, Ethernet, and D2D PHY IP.

Nice To Haves

Experience leading architecture and design of complex digital blocks and CPU subsystems from pre-silicon RTL to GDS2 signoff, through post-silicon FPGA prototyping, lab validation, and ATE bring-up.
Experience developing top- and block-level specifications for high-speed datapath and low-speed control planes, including power/timing budgeting, feedback/control system stability, and hardware-versus-firmware trade-offs.
Experience reviewing verification coverage metrics, independently debugging verification issues, supporting firmware-based verification/architecture, and integrating SerDes and DSP IP.
Hands-on experience with backend implementation activities, including synthesis, timing closure, DFT, low-power design, design automation scripting, and QOR metric processing.
Experience collaborating across cross-functional engineering teams to resolve technical trade-offs and complex design issues.

Responsibilities

Own the ASIC lifecycle from initial concept through tapeout and post-silicon production.
Lead cross-functional engineering teams across digital, analog, firmware, and physical design.
Define digital architectures.
Integrate high-speed IP, including ODSP, D2D IP, and SerDes XSR/PAM4.
Optimize power and performance for 100G, 200G, and 400G silicon photonics and Co-Packaged Optics.
Drive technical strategy and interconnect innovations.
Lead architecture and design of complex digital blocks and CPU subsystems from pre-silicon RTL through GDS2 signoff and post-silicon FPGA prototyping, lab validation, and ATE bring-up.
Develop top- and block-level specifications for high-speed datapath and low-speed control planes, including power and timing budgets, feedback/control system stability, and hardware-versus-firmware trade-offs.
Review verification coverage metrics, debug verification issues, support firmware-based verification and architecture, and integrate SerDes and DSP IP.
Perform backend implementation activities, including synthesis, timing closure, DFT, low-power design, design automation scripting, and QOR metric processing.
Collaborate across engineering teams to resolve technical trade-offs and complex design issues.

Benefits

Medical, dental, and vision insurance
401(k) plan with Cisco matching contribution
Paid parental leave
Short- and long-term disability coverage
Basic life insurance
Paid holidays and a floating holiday for non-exempt employees
Paid birthday day off, year-end holiday shutdown, and personal wellness days
Paid vacation or flexible vacation time off, depending on employee classification
Sick time off
Additional paid time away may be requested for critical or emergency family issues
Optional paid volunteer days
Annual bonuses for eligible non-sales employees
Potential eligibility for Cisco restricted stock unit grants