ASIC Design Intern

SK hynix • San Jose, CA

5d

About The Position

Join the System on Chip (SoC) Design Team at SK hynix Memory Solutions America, which develops controllers for high-performance SSDs. The team works across the design cycle, from micro-architecture and RTL design through timing closure and tapeout readiness, supporting enterprise and AI data center storage solutions. This is a six-month internship, 40 hours per week, based in San Jose, with a listed start of immediately (November 2026/December 2026). Compensation is $35–$45 per hour.

Requirements

• Currently enrolled in a BS, MS, or PhD program in Electrical Engineering, Computer Engineering, or a related field.
• Proficiency in logic design and micro-architecture.
• RTL coding proficiency in Verilog and/or SystemVerilog.

Nice To Haves

• Master’s or PhD in Electrical Engineering with working experience.
• Experience or coursework in digital logic design, verification methodologies, and protocols such as AMBA, PCIe, NAND, and DDR.
• Scripting skills in Python, Perl, or TCL, and Linux command-line experience.
• Strong problem-solving and communication skills.
• Proficiency in AI tools to generate synthesizable and functional RTL code.

Responsibilities

• Design RTL in Verilog/SystemVerilog for IP based on existing modules or new specifications.
• Collaborate with Design Verification, Silicon Validation, and Firmware teams, creating clear documentation and communication to ensure design quality.

What This Job Offers

• Career Level: Intern
• Education Level: No Education Listed