ASIC Digital Design Tech Lead

Cisco • Carlsbad, CA

1d

About The Position

As a Digital Design Technical Leader for Silicon One Optics, you will architect digital designs for next-generation optical interconnects and own the ASIC lifecycle from initial concept through tapeout and post-silicon production. You will lead cross-functional engineering teams across digital, analog, firmware, and physical design; define digital architectures; integrate high-speed IP including ODSP, D2D IP, and SerDes XSR/PAM4; and optimize power and performance for 100G, 200G, and 400G silicon photonics and Co-Packaged Optics. The role involves driving technical strategy and delivering silicon for high-performance computing.

Requirements

• Bachelor’s degree plus 8 years of related experience, or a master’s degree plus 6 years, or a Ph.D. plus 3 years.
• Digital design experience with FSMs, CPU subsystems, complex SoCs, and FPGA validation.
• Experience managing the complete ASIC/SoC design flow.
• Experience with bus and interface protocols such as SPI, I2C, APB, and AXI, as well as high-speed SerDes, Ethernet, and D2D PHY IP.

Nice To Haves

• Experience leading architecture and design of complex digital blocks and CPU subsystems from pre-silicon RTL through GDS2 signoff and post-silicon FPGA prototyping, lab validation, and ATE bring-up.
• Experience developing top- and block-level specifications for high-speed datapaths and low-speed control planes, including power/timing budgeting, feedback/control system stability, and hardware-versus-firmware trade-offs.
• Experience reviewing verification coverage metrics, independently debugging verification issues, supporting firmware-based verification and architecture, and integrating SerDes and DSP IP.
• Hands-on experience with backend implementation activities, including synthesis, timing closure, DFT, low-power design, design automation scripting, and QOR metric processing.
• Experience collaborating across cross-functional engineering teams to resolve technical trade-offs and complex design issues.

Responsibilities

• Own the ASIC lifecycle from initial concept through tapeout and post-silicon production.
• Lead cross-functional engineering teams across digital, analog, firmware, and physical design.
• Define digital architectures and integrate high-speed IP, including ODSP, D2D IP, and SerDes XSR/PAM4.
• Optimize power and performance for 100G, 200G, and 400G silicon photonics and Co-Packaged Optics.
• Lead architecture and design of complex digital blocks and CPU subsystems through pre-silicon RTL, GDS2 signoff, FPGA prototyping, lab validation, and ATE bring-up.
• Develop top- and block-level specifications for high-speed datapaths and low-speed control planes, including power and timing budgets, feedback/control system stability, and hardware-versus-firmware trade-offs.
• Review verification coverage metrics, debug verification issues, support firmware-based verification and architecture, and integrate SerDes and DSP IP.
• Perform backend implementation activities, including synthesis, timing closure, DFT, low-power design, design automation scripting, and QOR metric processing.
• Collaborate across engineering teams to resolve technical trade-offs and complex design issues.
• Drive technical strategy and interconnect innovations.

Benefits

• Medical insurance
• Dental insurance
• Vision insurance
• 401(k) plan with Cisco matching contribution
• Paid parental leave
• Short- and long-term disability coverage
• Basic life insurance
• Paid holidays
• Floating holiday for non-exempt employees
• Paid day off for employee’s birthday
• Paid year-end holiday shutdown
• Personal wellness days
• Vacation time or flexible vacation time off, depending on employee classification
• Sick time off
• Additional paid time away for critical or emergency family issues
• Optional paid volunteer days
• Annual bonuses for eligible non-sales roles
• Potential Cisco restricted stock unit grants

What This Job Offers

• Job Type: Full-time
• Career Level: Senior