ASIC Analog Layout Engineer

Micron • Minneapolis, MN

1d

About The Position

As an ASIC Analog Layout Engineer at Micron Technology, you will contribute to ASICs used in Micron’s tester and controller IP. The role focuses on the physical implementation of high-speed analog and mixed-signal circuits, partnering closely with analog designers to develop robust, manufacturable layout solutions that optimize performance, signal integrity, and reliability in advanced semiconductor technologies. Candidates with backgrounds in Analog Layout, Custom IC Layout, Mixed-Signal Layout, ASIC Physical Design, or Mask Design are encouraged to apply. Candidates meeting the minimum qualifications may be considered across multiple experience levels.

The position requires experience with custom analog, mixed-signal, or ASIC layouts and physical verification, along with knowledge of semiconductor processes and analog layout fundamentals. Preferred experience includes advanced process technologies, high-speed circuit blocks, parasitic analysis, layout automation, scripting, and AI-enabled productivity tools.

This is a full-time position. The estimated US base salary is $54.00–$92.00 per hour. Additional compensation may include benefits, bonuses, and equity. Micron offers medical, dental, and vision plans; income-protection programs; paid family leave; paid time off; and paid holidays.

Requirements

• Bachelor’s degree in Electrical Engineering or a related technical field, or equivalent industry experience.
• Experience using Cadence Virtuoso or similar custom IC layout tools to develop custom analog, mixed-signal, or ASIC layouts.
• Experience performing physical verification activities, including DRC, LVS, ERC, and antenna rule closure.
• Experience working with semiconductor process technologies and applying analog layout fundamentals to optimize circuit performance and manufacturability.

Nice To Haves

• Four or more years of experience in custom analog, mixed-signal, ASIC physical design, or IC layout engineering.
• Master’s degree in Electrical Engineering or a related technical field.
• Experience with advanced process technologies, including FinFET nodes of 16nm or below.
• Experience supporting high-speed analog circuits such as SerDes, PHY, PLL, DLL, TX, RX, clocking circuits, analog front-end designs, or related high-speed blocks.
• Experience with parasitic analysis and extraction tools such as Quantus Insight, ParagonX, or similar technologies.
• Experience developing automation solutions using SKILL, Python, PVL, or related scripting languages, including AI-enabled tools to improve engineering productivity and workflow efficiency.
• Experience with advanced-node layout techniques, including high-speed CMOS and CML layout methodologies.

Responsibilities

• Develop high-quality custom analog and mixed-signal layouts for high-speed ASIC applications.
• Collaborate with analog design engineers to create efficient, manufacturable layout solutions and provide feedback on layout feasibility.
• Perform and debug physical verification checks, including LVS, DRC, ERC, and antenna rule analysis.
• Optimize layouts for parasitics, signal integrity, electromigration, ESD robustness, and latch-up prevention.
• Contribute to layout methodologies, hierarchy standards, and process improvements that increase team efficiency.
• Develop automation, scripting, and AI-enabled solutions to improve layout productivity and workflow effectiveness.
• Troubleshoot and resolve layout environment, CAD, and tool-related issues.
• Support layout implementation for high-speed circuit blocks such as SerDes, PLL, DLL, transmitters, receivers, clocking circuits, analog front-end designs, and related PHY circuitry.

Benefits

• Medical, dental, and vision plans.
• Programs that help protect income in case of illness or injury.
• Paid family leave.
• Paid time off.
• Paid holidays.
• Additional compensation may include bonuses and equity.

What This Job Offers

• Job Type: Full-time