Analog Layout Engineer (eInfochips)

Arrow Electronics • US-TX-Texas (Remote Employees), TX

2d • Onsite

About The Position

The Analog Layout Engineer designs physical silicon layouts for high-frequency or high-speed mixed-signal circuits, including SerDes, ADCs, DACs, PLLs, and other high-speed blocks. The role involves floor planning and hierarchical integration at block and chip-top levels, as well as micro-bump or package-aware co-design. It also addresses parasitic and noise effects, layout-dependent effects, device matching, common-centroid structures, guard rings, and isolation or shielding techniques.

The engineer ensures closure of DRC, LVS, ERC, antenna rules, EM/IR reliability, and ESD protection. The position requires hands-on custom IC layout experience in deep-submicron or advanced CMOS/FinFET processes, with experience at lower nodes such as N3 or N5 identified as critical. The role is described as fully onsite and may require travel to an Arrow Client office at the request of client leadership. The posting also identifies the location as Austin, USA, and lists a remote-employees location in the Central Time Zone.

Requirements

• Generally 5 to 12+ years of hands-on custom IC layout experience in deep-submicron or advanced CMOS/FinFET nodes.
• Experience at lower nodes such as N3 or N5 is critical.
• Bachelor’s degree.
• Must be able to travel to an Arrow Client office location as requested by Arrow Client leadership.

Responsibilities

• Create block-level and chip-top-level floor plans.
• Manage hierarchical block integration.
• Handle micro-bump or package-aware co-design.
• Address layout-dependent effects (LOD, WPE, LDE), device matching, and common-centroid structures.
• Implement guard rings and isolation or shielding, including coaxial, differential, and ground shields.
• Ensure closure on DRC, LVS, ERC, antenna rules, EM/IR reliability, and ESD protection.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level