About The Position

Cadence is hiring a layout engineer for its custom layout team in the Cadence IP Group. The team creates high-quality, high-speed, high-accuracy CMOS integrated-circuit IP for consumer, industrial, and automotive markets, across multiple foundries and process nodes, including advanced FinFET and gate-all-around technologies. The role involves producing analog and mixed-signal circuit-block layouts in collaboration with circuit designers and contributing to all stages of the back-end flow, from initial floor planning through detailed layout and final verification against foundry design rules. The designer will use Cadence tools and may contribute to the development and validation of Cadence Virtuoso layout and verification software.

Requirements

  • BSEE or MSEE.
  • Exposure to microelectronics design and requirements.
  • Understanding of how layout affects circuit speed, capacitance, power, and area.
  • Knowledge of analog layout techniques such as matching and shielding.
  • Exposure to Cadence Virtuoso Layout and physical verification tools.
  • Team-oriented, driven, self-motivated, and autonomous.
  • Excellent communication, presentation, and customer service skills.

Responsibilities

  • Implement high-speed, high-accuracy cells, blocks, and IP blocks in a timely manner with quality and efficiency.
  • Collaborate with custom layout designers worldwide to build high-quality IP and test chips.
  • Work with circuit designers worldwide to understand technical and schedule needs.
  • Collaborate with Cadence R&D teams, including Virtuoso and PVS developers, to help develop layout-editing and verification tools.
  • Perform the back-end layout flow, including floor planning, detailed layout, and final verification of conformance to foundry design rules.
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