Cadence is seeking a layout engineer to create quality layouts for analog and mixed-signal circuit blocks in collaboration with circuit designers. The role covers the back-end design flow, from initial floor planning through detailed layout and final verification against foundry design rules. The team develops high-quality, high-speed and high-accuracy CMOS integrated-circuit IP for multiple foundries and process nodes, including FinFET and gate-all-around technologies. The designer will use Cadence design tools and work with experienced designers, global teams and Cadence R&D groups.
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Job Type
Full-time