Wireless SoC Design Engineer

Apple•San Diego, CA

About The Position

Join Apple’s wireless silicon development team, which develops highly energy-efficient wireless silicon and technologies that enhance the product-level user experience. The organization includes engineering teams across RF/analog, systems/PHY/MAC, VLSI/RTL, emulation, design verification, test and validation, and firmware/software. In this role, you will work on a small team designing CPU-based subsystems for high-performance, low-power wireless SoCs. You will work with SoC architects and IP developers to meet power, performance, and area goals for Apple devices, with particular focus on low-power metrics. You will participate in hardware/software/power partitioning discussions with software, firmware, and platform engineering teams, and integrate industry-standard and custom hardware IPs into SoCs. This highly visible position places you at the center of ASIC design efforts and involves collaboration across disciplines to help deliver products. The role includes writing micro-architecture and design specifications, developing RTL in SystemVerilog, integrating IP blocks, optimizing memories and hard macros, supporting verification at multiple levels, checking designs with static-analysis tools, and analyzing and optimizing area, timing, and power. You will collaborate with multidisciplinary teams to deliver designs on time and with high quality, incorporating appropriate checks throughout the design process.

Requirements

Bachelor of Science degree and 10+ years of relevant experience.
Familiarity with the ASIC design flow.
Knowledge of digital design, SoC architecture, and HDL languages such as Verilog.
Experience writing micro-architecture specifications and converting them to design.
Exposure to design methodologies and industry-standard EDA tools.
Experience with AXI/AHB bus fabric and processor subsystems.
Understanding of UPF and low-power design and implementation techniques.
Self-starter with a willingness to learn.

Responsibilities

Write micro-architecture and design specifications.
Code designs in SystemVerilog according to established design guidelines and own RTL development.
Integrate IP blocks and optimize memories and hard macros required for the block.
Support verification efforts at multiple levels.
Check designs using industry-standard static tools such as LINT, CDC, and RDC.
Analyze and optimize area, timing, and power.
Collaborate with multidisciplinary groups to deliver designs on time and with high quality, incorporating checks at each stage of the design process.
Work with SoC architects and IP developers to meet power, performance, and area goals.
Participate in hardware/software/power partitioning discussions with software, firmware, and platform engineering teams.
Integrate industry-standard and custom hardware IPs into SoCs.