VLSI Physical Design Engineer

Hewlett Packard Enterprise • Bloomington, CO

6d • $109,000 - $251,000 • Hybrid

About The Position

Hewlett Packard Enterprise is seeking a VLSI Physical Design Engineer to design, analyze, develop, modify, and evaluate VLSI components and hardware systems. The work includes determining architecture and logic design, verifying designs through software-based component and system simulation, and building physical implementations involving complex integrated-circuit layouts. The engineer will analyze designs, conduct experimental tests, and evaluate results to support prototype and production VLSI solutions.

In this role, you will apply subject-matter expertise to common and sometimes complex technical problems, recommend alternatives, exercise independent judgment, and may act as a project lead or assist less-experienced professionals. You will contribute to sophisticated ASIC products while partnering with teams across architecture, design, physical implementation, DFT, signal integrity, and related disciplines. The role is hybrid, with an average requirement of two days per week in an HPE office.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent.
• 1–6 years of experience in VLSI design, verification, or implementation.
• Knowledge of electrical engineering fundamentals, VLSI principles, digital logic, and computer architecture.
• Experience with one or more of the following: static timing analysis and timing signoff; timing constraints and validation; synthesis and netlist quality analysis; formal verification; floorplanning and chip partitioning; or ECO implementation.
• Experience with industry-standard EDA tools, such as Synopsys Fusion Compiler, Design Compiler, PrimeTime, or Formality, and/or Cadence RTL Compiler, Genus, or LEC.
• Strong analytical and problem-solving skills.
• Strong experience designing VLSI components, integrated circuitry, architectures, and algorithms.
• Ability to work independently and collaboratively across multiple engineering disciplines.
• Strong knowledge of programming and scripting, hardware description languages, electronic design automation (EDA), and/or FPGA tools.
• Coursework in VLSI design or VLSI concepts.
• Strong written and verbal communication skills, with mastery of English and the local language.
• Subject-matter knowledge in major areas of responsibility, growing breadth of understanding, and depth of specific expertise.

Responsibilities

• Perform static timing analysis for hierarchical designs at partition and full-chip levels.
• Create, validate, and maintain timing constraints and timing budgets for design and process requirements.
• Drive timing closure for partition-level and full-chip designs, including setup, hold, clock, I/O, and test timing.
• Analyze timing reports, identify critical paths, and implement fixes to achieve performance, power, and area objectives.
• Perform synthesis, netlist quality checks, and formal verification.
• Support chip partitioning, floorplanning, and physical design implementation.
• Create and manage functional engineering change orders (ECOs).
• Develop flow automation and methodology improvements for synthesis, timing analysis, formal verification, physical design, and signoff, often using AI to improve methodologies.
• Partner with cross-functional engineering teams to promote physical-design-aware architecture and implementation.
• Review design and project activities for compliance with ASIC technology, methodology, and development standards.
• Collaborate with external physical design partners to close timing and complete back-end flows.
• Provide technical guidance and mentoring to less-experienced engineers and contribute to continuous improvement across the design organization.

Benefits

• Comprehensive benefits supporting physical, financial, and emotional wellbeing for team members and their loved ones.
• Career-development programs to support professional goals.

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level