VLSI Physical Design Engineer

Hewlett Packard Enterprise • Fort Collins, CO

1d • $109,000 - $251,000 • Hybrid

About The Position

The VLSI Physical Design Engineer designs, analyzes, develops, modifies, and evaluates VLSI components and hardware systems. The role contributes to architecture and logic design, verification through simulation, and physical implementation of complex integrated circuits. It analyzes designs, conducts experimental tests, and evaluates results to support prototype and production VLSI solutions. The role applies subject matter expertise to common and sometimes complex technical problems, recommends alternatives, may lead projects, and may assist less-experienced professionals.

The engineer supports hierarchical and full-chip timing analysis and closure, synthesis, verification, partitioning, floorplanning, and physical implementation. The position partners with internal engineering teams and external physical-design partners to deliver reliable ASIC designs that meet performance, power, area, and development standards. It also develops automation and methodology improvements, including the use of AI, and provides technical guidance and mentoring.

This hybrid role requires working an average of two days per week from an HPE office. The listed U.S. base salary ranges are $115,000–$218,000 annually in Colorado and $109,000–$251,000 in Minnesota and Wisconsin; variable incentives may also be offered. Actual offers may vary by location, experience, education, training, and skill level.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent.
• 1–6 years of experience in VLSI design, verification, or implementation.
• Strong knowledge of electrical engineering fundamentals, VLSI principles, digital logic, and computer architecture.
• Experience with one or more of the following: static timing analysis and timing signoff; timing constraints and validation; synthesis and netlist quality analysis; formal verification; floorplanning and chip partitioning; or ECO implementation.
• Experience with industry-standard EDA tools such as Synopsys Fusion Compiler, Design Compiler, PrimeTime, or Formality, and/or Cadence RTL Compiler, Genus, or LEC.
• Strong analytical and problem-solving skills.
• Strong experience designing VLSI components, integrated circuitry, architectures, and algorithms.
• Ability to work independently and collaboratively across multiple engineering disciplines.
• Strong knowledge of programming and scripting, hardware description languages, electronic design automation (EDA), and/or FPGA tools.
• Coursework in VLSI design or VLSI concepts.
• Strong written and verbal communication skills; mastery of English and the local language.
• Subject matter knowledge in major areas of responsibility, with growing breadth of understanding and depth of specific expertise.

Responsibilities

• Perform static timing analysis for hierarchical designs at partition and full-chip levels.
• Create, validate, and maintain timing constraints and timing budgets for design and process requirements.
• Drive timing closure for partition-level and full-chip designs, including setup, hold, clock, I/O, and test timing.
• Analyze timing reports, identify critical paths, and implement fixes to meet performance, power, and area objectives.
• Perform synthesis, netlist quality checks, and formal verification.
• Support chip partitioning, floorplanning, and physical design implementation.
• Create and manage functional engineering change orders (ECOs).
• Develop flow automation and methodology improvements for synthesis, timing analysis, formal verification, physical design, and signoff, including using AI to improve methodologies.
• Partner with cross-functional engineering teams to promote physical-design-aware architecture and implementation.
• Review design and project activities for compliance with ASIC technology, methodology, and development standards.
• Collaborate with external physical design partners to close timing and complete back-end flows.
• Provide technical guidance and mentoring to less-experienced engineers and contribute to continuous improvement across the design organization.

Benefits

• Health and wellbeing benefits supporting physical, financial, and emotional wellbeing.
• Personal and professional development programs to support career goals.

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level