VLSI Physical Design Engineer

Hewlett Packard Enterprise • Fort Collins, CO

1d • $109,000 - $251,000 • Hybrid

About The Position

Hewlett Packard Enterprise is hiring a VLSI Physical Design Engineer to design, analyze, develop, modify, and evaluate VLSI components and hardware systems. The role includes determining architecture and logic design, verifying designs through software-based component and system simulation, and building physical implementations involving complex integrated-circuit layouts. It also involves analyzing designs, conducting experimental tests, and evaluating results to support prototype and production VLSI solutions. The position may lead project work and assist less-experienced professionals, applying subject matter expertise and independent judgment to solve technical problems and recommend alternatives.

This hybrid position requires working an average of two days per week from an HPE office. The engineer will perform static timing analysis at partition and full-chip levels; create and maintain timing constraints and budgets; and drive timing closure across setup, hold, clock, I/O, and test timing. The role also supports synthesis, formal verification, chip partitioning, floorplanning, physical design implementation, engineering change orders, automation, methodology development, and collaboration with internal and external engineering partners. The listed annual base salary ranges are USD 115,000–218,000 in Colorado and USD 109,000–251,000 in Minnesota and Wisconsin. Variable incentives may also be offered.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent.
• 1–6 years of experience in VLSI design, verification, or implementation.
• Strong knowledge of electrical engineering fundamentals, VLSI principles, digital logic, and computer architecture.
• Experience with one or more of the following: static timing analysis and timing signoff; timing constraints and validation; synthesis and netlist quality analysis; formal verification; floorplanning and chip partitioning; or ECO implementation.
• Experience with industry-standard EDA tools, such as Synopsys Fusion Compiler, Design Compiler, PrimeTime, or Formality, and/or Cadence RTL Compiler, Genus, or LEC.
• Strong analytical and problem-solving skills.
• Knowledge of programming and scripting, hardware description languages, electronic design automation (EDA), and/or FPGA tools.
• Coursework in VLSI design or VLSI concepts.
• Strong written and verbal communication skills; mastery in English and the local language.
• Ability to work independently and collaboratively across multiple engineering disciplines.

Nice To Haves

• Experience with hierarchical timing analysis and full-chip timing closure.
• Experience with clock, I/O, test, and other specialized timing-closure challenges.
• Experience developing ASIC implementation flows, automation, and design methodologies.
• Experience working with advanced process technologies and complex, high-performance ASIC designs.
• Experience using AI tools and methodologies to run design experiments, learn new information, and optimize flows.
• Demonstrated ability to provide technical leadership, mentor engineers, and influence cross-functional design decisions.
• Publications, patents, or other demonstrated contributions in ASIC, VLSI, physical design, or electronic design automation.

Responsibilities

• Perform static timing analysis for hierarchical designs at partition and full-chip levels.
• Create, validate, and maintain timing constraints and timing budgets for design and process requirements.
• Drive timing closure for partition-level and full-chip designs, including setup, hold, clock, I/O, and test timing.
• Analyze timing reports, identify critical paths, and implement fixes to meet performance, power, and area objectives.
• Perform synthesis, netlist quality checks, and formal verification.
• Support chip partitioning, floorplanning, and physical design implementation.
• Create and manage functional engineering change orders (ECOs).
• Develop flow automation and methodology improvements for synthesis, timing analysis, formal verification, physical design, and signoff, including use of AI to improve methodologies.
• Partner with cross-functional engineering teams to promote physical-design-aware architecture and implementation.
• Review design and project activities for compliance with ASIC technology, methodology, and development standards.
• Collaborate with external physical design partners to close timing and complete back-end flows.
• Provide technical guidance and mentoring to less-experienced engineers and contribute to continuous improvement across the design organization.
• May direct support personnel in preparing detailed designs, design testing, and prototype fabrication.

Benefits

• Comprehensive benefits supporting physical, financial, and emotional wellbeing for team members and their loved ones.
• Career development programs supporting professional growth and career goals.
• Variable incentives may also be offered.

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level