VLSI CAD Engineer

Apple • Cupertino, CA

3d • $154,271 - $225,300

About The Position

Apple Inc. is hiring a VLSI CAD Engineer to work in Cupertino, California, and various unanticipated locations throughout the United States. The role focuses on executing and improving RTL regression testing and verification systems. The engineer will use Verilog/SystemVerilog HDL simulators, UVM-based verification environments, coverage tools, and RTL debuggers to monitor results, analyze coverage, investigate failed tests, and collaborate with the design verification team on root causes.

The position also develops automation and machine-learning solutions to improve verification efficiency and computer-resource usage. Work includes building models to predict test failures and optimize resource allocation or scheduling, applying task parallelism or cloud-based platforms to improve regression performance, and maintaining reliable RTL regression infrastructure. The role is 40 hours per week.

Requirements

• Master’s degree or foreign equivalent in Electrical Engineering or a related field.
• At least 2 years of experience in the job offered or a related occupation.
• Experience executing RTL regression tests using Verilog/SystemVerilog HDL simulators and UVM-based verification environments.
• Experience building and maintaining self-retraining machine-learning pipelines for automated test-case generation, with scheduled daily triggers and continuous monitoring of data-quality metrics and runtime-performance fluctuations.
• Experience using RTL debuggers to step through HDL code and identify root causes of regression failures.
• Experience developing automation scripts for regression setup, execution, and result analysis.
• Experience building machine-learning models to predict test failures and optimize resource allocation in verification workflows.
• Experience implementing performance optimizations using task parallelism libraries or cloud-based verification platforms.
• Experience applying machine-learning techniques to optimize test scheduling and identify critical code paths for focused verification.
• Experience maintaining and enhancing RTL regression infrastructure to ensure verification-system reliability and efficiency.

Responsibilities

• Execute RTL regression tests using Verilog/SystemVerilog HDL simulators and system verification languages such as UVM.
• Monitor regression results, analyze coverage data, and identify failed tests.
• Use coverage tools to measure and enhance functional coverage.
• Collaborate with the design verification team to investigate the root causes of regression failures.
• Use RTL debuggers to step through code and identify issues.
• Develop solutions to address regression issues, improve verification efficiency, and optimize computer usage using machine-learning techniques.
• Build machine-learning models to predict test failures and optimize resource allocation.
• Improve regression-run performance using task parallelism libraries or cloud-based verification platforms.
• Maintain and enhance the RTL regression system to ensure reliability and efficiency.
• Create automation scripts for regression setup, execution, and result analysis.
• Explore and apply machine-learning techniques to optimize computer usage in regression testing.
• Predict test failure rates by building models, optimizing test scheduling, or identifying critical code paths for focused verification.

Benefits

• Comprehensive medical and dental coverage.
• Retirement benefits.
• Discounted products and free services.
• Reimbursement for certain education expenses, including tuition, for formal education related to advancing a career at Apple.
• Potential eligibility for discretionary bonuses or commission payments.
• Potential relocation assistance.
• Opportunity to participate in discretionary restricted stock unit awards.
• Opportunity to purchase Apple stock at a discount through the Employee Stock Purchase Plan.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level