Apple Inc. is hiring a VLSI CAD Engineer in Cupertino, California, and various unanticipated locations throughout the USA. The role focuses on executing and improving RTL regression testing and verification infrastructure. The engineer will use industry-standard Verilog/SystemVerilog HDL simulators and UVM-based verification environments, analyze regression results and coverage data, and collaborate with the design verification team to diagnose failures. The position also develops machine-learning solutions to predict test failures, improve test scheduling, allocate computing resources, and identify critical code paths for focused verification. It includes optimizing regression performance with task-parallelism libraries or cloud-based verification platforms, maintaining and enhancing regression systems, and building automation for regression setup, execution, and result analysis. The role is 40 hours per week.
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Job Type
Full-time
Career Level
Mid Level