VLSI CAD Timing Intern, Applied AI - Summer 2027
About The Position
NVIDIA is seeking a VLSI CAD Timing Intern focused on Applied AI to help develop end-to-end solutions for timing and constraint analysis workflows. The work spans data generation, model training, orchestration, and agentic automation. The intern will join a cross-disciplinary team building intelligent systems that learn from sign-off data, reason across flows, and help engineers achieve faster and more predictable closure. The intern will learn and support static timing analysis (STA) flows for advanced ASIC designs, help automate timing, constraints, and quality-of-results (QoR) validation, and assist with analysis of timing reports, constraints, and design data across corners and modes. The role also involves collaborating with CAD, physical design, and methodology engineers on timing sign-off strategies, contributing to early AI- or analytics-assisted timing approaches, and exploring how physical effects influence timing and design decisions.
Requirements
- Currently pursuing a Master's or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Coursework or academic knowledge in VLSI/ASIC design, digital circuits, or computer architecture.
- Exposure to applying agentic AI to back-end VLSI tasks, such as floorplanning, timing closure, or physical verification.
- Familiarity with the basics of static timing analysis, constraints, or digital design flows.
- Knowledge of scripting or programming; Python is preferred.
- Comfort working with data, reports, and technical problem-solving in complex systems.
Nice To Haves
- Academic projects, research, or internships related to VLSI, physical design, STA, or EDA tools.
- Exposure to TCL.
- Exposure to machine learning, data analysis, or AI concepts applied to engineering problems.
- Experience automating workflows, analyzing large datasets, or contributing to technical tools or open-source projects.
Responsibilities
- Learn and support static timing analysis (STA) flows using industry tools such as PrimeTime and Tempus for advanced ASIC designs.
- Help develop and automate timing, constraints, and QoR validation flows using scripting and data-driven methods.
- Assist with analyzing timing reports, constraints, and design data across corners and modes to improve closure predictability.
- Collaborate with CAD, physical design, and methodology engineers on timing sign-off strategies and best practices.
- Contribute to early AI- or analytics-assisted approaches for timing analysis, constraint checking, or flow optimization.
- Explore how physical effects, including IR drop, crosstalk, aging, and thermal impact, influence timing and design decisions.
Benefits
- Eligible for intern benefits; specific benefits are not listed.
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What This Job Offers
Career Level
Intern
